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/arch/powerpc/platforms/cell/spufs/
Dfault.c113 u64 ea, dsisr, access; in spufs_handle_class1() local
145 access = (_PAGE_PRESENT | _PAGE_USER); in spufs_handle_class1()
146 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL; in spufs_handle_class1()
148 ret = hash_page(ea, access, 0x300); in spufs_handle_class1()
/arch/arm/mach-omap2/
Dusb-tusb6010.c77 t.access = next_clk(t.oe_on, tmp, fclk_ps); in tusb_set_async_mode()
80 tmp = t.access * 1000; in tusb_set_async_mode()
81 t.oe_off = next_clk(t.access, tmp, fclk_ps); in tusb_set_async_mode()
144 t.access = next_clk(t.oe_on, tmp, fclk_ps); in tusb_set_sync_mode()
147 tmp = (t.access * 1000) + (1 * fclk_ps); in tusb_set_sync_mode()
148 t.oe_off = next_clk(t.access, tmp, fclk_ps); in tusb_set_sync_mode()
/arch/arm/mach-iop32x/include/mach/
Dentry-macro.S18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
35 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/arm/mach-iop13xx/include/mach/
Dentry-macro.S25 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
44 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/arm/mach-iop33x/include/mach/
Dentry-macro.S18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
36 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/arch/x86/kvm/
Dpaging_tmpl.h119 unsigned access; in FNAME() local
121 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; in FNAME()
124 access &= ~(gpte >> PT64_NX_SHIFT); in FNAME()
126 return access; in FNAME()
268 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte); in FNAME()
277 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0, in FNAME()
293 unsigned access = gw->pt_access; in FNAME() local
303 mmu_set_spte(vcpu, sptep, access, gw->pte_access & access, in FNAME()
325 access &= ~ACC_WRITE_MASK; in FNAME()
332 metaphysical, access, sptep); in FNAME()
[all …]
Di8254.c342 int channel, access; in pit_ioport_write() local
371 access = (val >> 4) & KVM_PIT_CHANNEL_MASK; in pit_ioport_write()
372 if (access == 0) { in pit_ioport_write()
375 s->rw_mode = access; in pit_ioport_write()
376 s->read_state = access; in pit_ioport_write()
377 s->write_state = access; in pit_ioport_write()
/arch/avr32/mach-at32ap/
DKconfig12 when doing little-endian port access.
16 raw access and is thus not affected by any of this.)
/arch/cris/arch-v32/lib/
Dchecksumcopy.S29 1: ;; A failing userspace access (the read) will have this as PC.
70 2: ;; A failing userspace access for the read below will have this as PC.
86 3: ;; A failing userspace access for the read below will have this as PC.
Dcsumcpfruser.S45 ;; Signal in *errptr that we had a failing access.
/arch/powerpc/include/asm/
Dmmu-hash64.h268 extern int __hash_page_4K(unsigned long ea, unsigned long access,
271 extern int __hash_page_64K(unsigned long ea, unsigned long access,
275 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
276 extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
/arch/s390/kernel/
Dhead31.S50 .long 0 # cr8: access registers translation
70 .long 0x80000000,0,0,0 # invalid access-list entries
93 lam 0,15,.Laregs-.LPG3(%r13) # load access regs needed by uaccess
/arch/powerpc/mm/
Dhash_utils_64.c855 int hash_page(unsigned long ea, unsigned long access, unsigned long trap) in hash_page() argument
866 ea, access, trap); in hash_page()
917 return hash_huge_page(mm, access, ea, vsid, local, trap); in hash_page()
946 if (access & ~pte_val(*ptep)) { in hash_page()
997 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); in hash_page()
1002 if (access & spp) in hash_page()
1005 rc = __hash_page_4K(ea, access, vsid, ptep, trap, in hash_page()
1021 unsigned long access, unsigned long trap) in hash_preload() argument
1040 " trap=%lx\n", mm, mm->pgd, ea, access, trap); in hash_preload()
1076 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); in hash_preload()
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Dmmu_decl.h69 unsigned long access, unsigned long trap);
/arch/cris/arch-v10/lib/
Dchecksumcopy.S40 1: ;; A failing userspace access will have this as PC.
103 2: ;; A failing userspace access will have this as PC.
122 3: ;; A failing userspace access will have this as PC.
Dcsumcpfruser.S45 ;; Signal in *errptr that we had a failing access.
/arch/m68k/ifpsp060/src/
Disp.S889 # future access error; if -(a7), set mda7_flg in #
893 # future access error; if (a7)+, set mia7_flg in #
1045 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1056 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1067 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1078 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1089 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1100 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1111 mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
1130 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error
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/arch/powerpc/platforms/ps3/
DKconfig26 This gives you access to some advanced options for the PS3. The
102 This support is required to access the PS3 hard disk.
112 This support is required to access the PS3 BD/DVD/CD-ROM drive.
123 This support is required to access the PS3 FLASH ROM, which
/arch/arm/kernel/
Dcrunch-bits.S71 tst r1, #0x00800000 @ access to crunch enabled?
75 orr r1, r1, #0x00800000 @ enable access to crunch
219 ldr r5, [r4, #0x80] @ enable access to crunch
231 mov r2, #0xaa @ disable access to crunch
Diwmmxt.S64 orr r2, r2, #0x3 @ enable access to CP0 and CP1
183 orr r4, r4, #0x3 @ enable access to CP0 and CP1
191 bic r4, r4, #0x3 @ disable access to CP0 and CP1
290 1: eor r1, r1, #3 @ flip Concan access
/arch/x86/
DKconfig.debug9 bool "Filter access to /dev/mem"
11 If this option is disabled, you allow userspace (root) access to all
13 access to this is obviously disastrous, but specific access can
19 userspace access to PCI space and the BIOS code and data regions.
84 bool "Debug access to per_cpu maps"
/arch/parisc/math-emu/
DREADME4 someone in the future, with access to HP-UX source code, is generous
/arch/
DKconfig52 unaligned access and require fixing it up in the exception
62 See Documentation/unaligned-memory-access.txt for more
/arch/arm/plat-omap/include/mach/
Dgpmc.h84 u16 access; /* Start-cycle to first data valid delay */ member
/arch/arm/mach-ixp4xx/
DKconfig171 bool "Use indirect PCI memory access"
177 To access PCI via this space, we simply ioremap() the BAR
184 configured to use indirect registers to access PCI This allows
186 The disadvantage of this is that every PCI access requires

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