| /arch/mips/kernel/ |
| D | relocate_kernel.S | 26 and s3, s2, 0x1
28 and s4, s2, ~0x1 /* store destination addr in s4 */
34 and s3, s2, 0x2
36 and s0, s2, ~0x2
41 and s3, s2, 0x4
46 and s3, s2, 0x8
48 and s2, s2, ~0x8
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| D | entry.S | 46 # between sampling and return
72 local_irq_disable # make sure need_resched and
74 # sampling and return
77 and t0, a2, t0
127 and v0, ST0_IEP
129 and v0, ST0_IE
150 local_irq_disable # make sure need_resched and
152 # sampling and return
160 work_notifysig: # deal with pending signals and
171 and t0, a2 # a2 is preloaded with TI_FLAGS
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| /arch/arm/mm/ |
| D | abort-lv4t.S | 25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
34 and r7, r8, #15 << 24
66 and r6, r8, r7
67 and r2, r8, r7, lsl #1
69 and r2, r8, r7, lsl #2
71 and r2, r8, r7, lsl #3
75 and r6, r6, #15 @ r6 = no. of registers to transfer.
76 and r5, r8, #15 << 16 @ Extract 'n' from instruction
88 and r5, r8, #0x00f @ get Rm / low nibble of immediate value
94 and r5, r8, #15 << 16 @ Extract 'n' from instruction
[all …]
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| /arch/mn10300/mm/ |
| D | cache-mn10300.S | 47 and ~EPSW_IE,epsw
52 and ~CHCTR_ICEN,d0
55 # and wait for it to calm down
72 # and reenable it
73 and ~CHCTR_ICINV,d0
98 and ~EPSW_IE,epsw
103 and ~CHCTR_DCEN,d0
106 # and wait for it to calm down
123 # and reenable it
124 and ~CHCTR_DCINV,d0
[all …]
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| D | tlb-mn10300.S | 9 # This program is free software; you can redistribute it and/or
30 and ~EPSW_NMID,epsw
44 and 0xffc00000,d2
60 and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
82 and ~EPSW_NMID,epsw
96 and 0xffc00000,d2
112 and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
133 and ~EPSW_NMID,epsw
195 and PAGE_MASK,d0
201 and ~EPSW_NMID,epsw
|
| /arch/arm/mach-pnx4008/ |
| D | sleep.S | 33 @ and put it's value in r5
49 and r5, r5, #(~(1 << 8))
51 and r5, r5, #(~(1 << 9))
66 and r5, r5, #(~(1 << 8))
70 and r5, r5, #(~(1 << 9))
98 @ clear STOP mode and SDRAM self-refresh bits
106 @ restore regs and return
117 @ and put it's value in r5
133 and r5, r5, #(~(1 << 8))
135 and r5, r5, #(~(1 << 9))
[all …]
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| /arch/um/ |
| D | Kconfig.char | 22 information and command line examples of how to use this facility.
29 This option enables support for attaching UML consoles and serial
31 and there is never any data to be read.
36 This option enables support for attaching UML consoles and serial
38 <port number>'. Any number of consoles and serial lines may be
46 This option enables support for attaching UML consoles and serial
48 pseudo-terminals (/dev/pty*) and pts pseudo-terminals are controlled
56 This option enables support for attaching UML consoles and serial
58 (/dev/tty*) and the slave side of pseudo-terminals (/dev/ttyp* and
65 This option enables support for attaching UML consoles and serial
[all …]
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| /arch/m68k/ifpsp060/ |
| D | TEST.DOC | 9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
32 The files itest.sa and ftest.sa contain simple tests to check
33 the state of the 68060ISP and 68060FPSP once they have been installed.
37 The release files itest.sa and ftest.sa are essentially
[all …]
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| /arch/alpha/lib/ |
| D | strncat.S | 41 and $2, $3, $2
43 and $2, 0xf0, $3 # binary search for that set bit
44 and $2, 0xcc, $4
45 and $2, 0xaa, $5
67 and $24, 0x80, $2 # no zero next byte
|
| D | strcat.S | 35 and $2, $3, $2
37 and $2, 0xf0, $3 # binary search for that set bit
38 and $2, 0xcc, $4
39 and $2, 0xaa, $5
|
| D | strlen.S | 40 and $2, $3, $2
42 and $2, 0x0f, $1
46 and $2, 0x33, $1
50 and $2, 0x55, $1
|
| /arch/m68k/fpsp040/ |
| D | README | 9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 PARTICULAR PURPOSE and any warranty against infringement with
15 and any accompanying written materials.
23 and support of the SOFTWARE.
25 You are hereby granted a copyright license to use, modify, and
27 without alteration in any modified and/or redistributed versions,
28 and that such modified versions are clearly identified as such.
|
| D | x_operr.S | 163 bsr check_upper |check if exp and ms mant are special
168 bra not_enabled |clean and exit
190 bsr check_upper |check if exp and ms mant are special
195 bra not_enabled |clean and exit
212 | and aiop and write the portion of the nan to memory for the
223 | the operr and aiop bits, and clears inex and ainex, incorrectly
273 | and call mem_write.
282 | Check the exponent for $c000 and the upper 32 bits of the
284 | and store the lower n bits of the least lword of FPTEMP
285 | to d0 for write out. If not, it is a real operr, and set d0.
[all …]
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| D | bugfix.S | 93 | FRESTORE and return;
143 | FRESTORE and return;
148 | FRESTORE and return;
172 | Simply branch to fix_done and exit normally.
191 | Check for opclass 0. If not, go and check for opclass 2 and sgl.
197 | Check for cu and nu register conflict. If one exists, this takes
198 | priority over a cu and xu conflict.
205 | Check for cu dest equal to nu dest. If so, go and fix the
212 | Check for cu and xu register conflict.
247 | dest and the dest of the xu. We must clear the instruction in
[all …]
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| /arch/sparc/lib/ |
| D | strncmp_32.S | 24 and %o3, 0xff, %o0
40 and %o3, 0xff, %o0
56 and %o3, 0xff, %o0
72 and %o3, 0xff, %o0
92 and %o2, 3, %o2
97 and %o3, 0xff, %o0
116 and %g2, 0xff, %o0
|
| D | bitops.S | 18 and %o0, 63, %g2
26 and %g7, %o2, %g2
41 and %o0, 63, %g2
49 and %g7, %o2, %g2
64 and %o0, 63, %g2
72 and %g7, %o2, %g2
87 and %o0, 63, %g2
108 and %o0, 63, %g2
129 and %o0, 63, %g2
|
| /arch/m32r/lib/ |
| D | strlen.S | 29 sub r0, r5 || and r4, r7
30 and r4, r0
33 sub r1, r5 || and r4, r7
34 and r4, r1 || addi r2, #4
78 and r4, r7 ; return 0;
79 and r4, r0
86 and r4, r7 ; return 0;
87 and r4, r1
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| /arch/cris/arch-v32/boot/compressed/ |
| D | README | 7 by that makefile into text and data binary files, vmlinux.text and
10 Those files together with a ROM filesystem can be catted together and
13 They can also be catted together and compressed with gzip, which is what
21 assumes the DRAM starts at 0x40000000 and that it is at least 8 MB,
22 so it puts its code at 0x40700000, and initial stack at 0x40800000.
|
| /arch/cris/arch-v10/boot/compressed/ |
| D | README | 8 by that makefile into text and data binary files, vmlinux.text and
11 Those files together with a ROM filesystem can be catted together and
14 They can also be catted together and compressed with gzip, which is what
22 assumes the DRAM starts at 0x40000000 and that it is at least 8 MB,
23 so it puts its code at 0x40700000, and initial stack at 0x40800000.
|
| /arch/arm/nwfpe/ |
| D | softfloat-macros | 14 overseen by Profs. Nelson Morgan and John Wawrzynek. More information
25 (1) they include prominent notice that the work is derivative, and (2) they
87 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
91 shifted off is the most-significant bit of the extra result, and the other
92 63 bits of the extra result are all zero if and only if _all_but_the_last_
95 (This routine makes more sense if `a0' and `a1' are considered to form a
96 fixed-point value with binary point between `a0' and `a1'. This fixed-point
97 value is shifted right by the number of bits given in `count', and the
100 described above, and is returned at the location pointed to by `z1Ptr'.)
134 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
[all …]
|
| /arch/arm/mach-shark/include/mach/ |
| D | entry-macro.S | 25 and \irqstat, \irqnr, #0x80
28 and \irqnr, \irqnr, #7
34 and \irqstat, \irqnr, #0x80
37 and \irqnr, \irqnr, #7
|
| /arch/cris/arch-v10/lib/ |
| D | dram_init.S | 20 ;; WARNING! The registers r8 and r9 are used as parameters carrying
56 and.d 0x00ff0000, $r2
60 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
63 and.d 0x03, $r1 ; Get CAS latency
64 and.d 0x1000, $r3 ; 50 or 100 MHz?
81 and.d 0x800000, $r1 ; DRAM width is bit 23
89 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
104 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
106 and.d 0x000fffff, $r3
|
| /arch/arm/mach-mx3/ |
| D | Kconfig | 9 configurations for the board and its peripherals.
15 specific configurations for the board and its peripherals.
22 configurations for the board and its peripherals.
29 configurations for the board and its peripherals.
36 configurations for the board and its peripherals.
|
| /arch/arm/lib/ |
| D | io-readsw-armv3.S | 47 and r3, r3, ip
52 and r4, r4, ip
57 and r5, r5, ip
62 and r6, r6, ip
78 and r3, r3, ip
83 and r4, r4, ip
93 and r3, r3, ip
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| /arch/powerpc/platforms/iseries/ |
| D | Kconfig | 15 If you are running on an iSeries system and you want to use
16 virtual disks created and managed by OS/400, say Y.
22 If you are running Linux on an IBM iSeries system and you want to
29 If you are running Linux on an iSeries system and you want Linux
30 to read and/or write a tape drive owned by OS/400, say Y here.
|