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Searched refs:clk_h (Results 1 – 11 of 11) sorted by relevance

/arch/arm/mach-ep93xx/
Dclock.c36 static struct clk clk_h; variable
53 INIT_CK(NULL, "hclk", &clk_h),
125 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; in ep93xx_clock_init()
126 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; in ep93xx_clock_init()
141 clk_f.rate / 1000000, clk_h.rate / 1000000, in ep93xx_clock_init()
/arch/arm/plat-s3c64xx/
Dclock.c100 .parent = &clk_h,
162 .parent = &clk_h,
174 .parent = &clk_h,
180 .parent = &clk_h,
186 .parent = &clk_h,
192 .parent = &clk_h,
Ds3c6400-clock.c611 clk_h.rate = hclk; in s3c6400_setup_clocks()
/arch/arm/mach-s3c2412/
Dclock.c148 else if (parent == &clk_h) in s3c2412_setparent_usbsrc()
241 else if (parent == &clk_h) in s3c2412_setparent_armclk()
403 else if (parent == &clk_h) in s3c2412_setparent_cam()
453 .parent = &clk_h,
493 .parent = &clk_h,
499 .parent = &clk_h,
505 .parent = &clk_h,
511 .parent = &clk_h,
517 .parent = &clk_h,
529 .parent = &clk_h,
[all …]
/arch/arm/mach-s3c2443/
Dclock.c264 else if (parent == &clk_h) in s3c2443_setparent_armclk()
697 .parent = &clk_h,
741 .parent = &clk_h,
747 .parent = &clk_h,
753 .parent = &clk_h,
759 .parent = &clk_h,
765 .parent = &clk_h,
771 .parent = &clk_h,
777 .parent = &clk_h,
789 .parent = &clk_h,
[all …]
/arch/arm/plat-s3c24xx/
Ds3c2410-clock.c94 .parent = &clk_h,
134 .parent = &clk_h,
146 .parent = &clk_h,
152 .parent = &clk_h,
Ds3c244x-clock.c53 else if (parent == &clk_h) in s3c2440_setparent_armclk()
84 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f; in s3c244x_clk_add()
Dclock.c56 clk_h.rate = hclk; in s3c24xx_setup_clocks()
Dclock-dclk.c138 else if (parent == &clk_h) in s3c24xx_clkout_setparent()
/arch/arm/plat-s3c/include/plat/
Dclock.h44 extern struct clk clk_h;
/arch/arm/plat-s3c/
Dclock.c273 struct clk clk_h = { variable
360 if (s3c24xx_register_clock(&clk_h) < 0) in s3c24xx_register_baseclocks()