Searched refs:cores (Results 1 – 8 of 8) sorted by relevance
81 unsigned numnodes, cores, bits, apicid_base; in k8_scan_nodes() local198 cores = (1<<bits); in k8_scan_nodes()215 for (j = apicid_base; j < cores + apicid_base; j++) in k8_scan_nodes()
80 # All cores other than the master need to wait here for SMP bootstrap112 # Someone tried to boot SMP with a non SMP kernel. All extra cores
8 The Freescale E600 SoCs have 74xx cores.
182 # All 405-based cores up until the 405GPR and 405EP have this errata.186 # All 40x-based cores, up until the 405GPR and 405EP have this errata.
127 and some e300 cores (c3 and c4). Select this only if your140 addresses. This feature may not be available on all cores.
355 bool "Accept early Feroceon cores with an ARM926 ID"359 This enables the usage of some old Feroceon cores632 Some cores are synthesizable to have various sized cache. For
296 a variety of MIPS cores.1266 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.1544 when dealing with MIPS MT enabled cores at a cost of slightly
383 # the right-hand clause are the cores that benefit from this optimization.