Searched refs:dcr (Results 1 – 25 of 39) sorted by relevance
12
86 unsigned long dcr; in dmabrg_irq() local89 dcr = ctrl_inl(DMABRGCR); in dmabrg_irq()90 ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ in dmabrg_irq()91 dcr &= dcr >> 8; /* ignore masked */ in dmabrg_irq()94 if (dcr & 1) in dmabrg_irq()96 if (dcr & 2) in dmabrg_irq()100 dcr >>= 16; in dmabrg_irq()101 while (dcr) { in dmabrg_irq()102 i = __ffs(dcr); in dmabrg_irq()103 dcr &= dcr - 1; in dmabrg_irq()[all …]
40 dcr = 1 define42 mfdcr r3,dcr; blr43 mtdcr dcr,r4; blr44 dcr = dcr + 1 define
11 obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o46 obj-$(CONFIG_PPC_DCR) += dcr.o
23 dcr-parent = <0x1>;44 dcr-controller;45 dcr-access-method = "native";59 dcr-reg = <0xc0 0x9>;75 dcr-reg = <0x10 0x2>;80 dcr-reg = <0x180 0x62>;93 dcr-reg = <0xa0 0x5>;140 dcr-reg = <0x12 0x2>;
19 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";54 dcr-reg = <0x0c0 0x009>;64 dcr-reg = <0x0d0 0x009>;74 dcr-reg = <0x00e 0x002>;79 dcr-reg = <0x00c 0x002>;91 dcr-reg = <0x010 0x002>;96 dcr-reg = <0x100 0x027>;101 dcr-reg = <0x180 0x062>;[all …]
20 dcr-parent = <&{/cpus/cpu@0}>;43 dcr-controller;44 dcr-access-method = "native";58 dcr-reg = <0x200 0x009>;69 dcr-reg = <0x0c0 0x009>;82 dcr-reg = <0x0d0 0x009>;94 dcr-reg = <0x210 0x009>;105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */128 dcr-reg = <0x010 0x002>;[all …]
21 dcr-parent = <&{/cpus/cpu@0}>;44 dcr-controller;45 dcr-access-method = "native";58 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x0d0 0x009>;79 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;92 dcr-reg = <0x010 0x002>;98 dcr-reg = <0x020 0x008 0x00a 0x001>;104 dcr-reg = <0x100 0x027>;109 dcr-reg = <0x180 0x062>;[all …]
38 dcr-parent = <&{/cpus/cpu@0}>;61 dcr-controller;62 dcr-access-method = "native";75 dcr-reg = <0x0c0 0x009>;85 dcr-reg = <0x0d0 0x009>;97 dcr-reg = <0x0e0 0x009>;109 dcr-reg = <0x0f0 0x009>;119 dcr-reg = <0x00e 0x002>;124 dcr-reg = <0x00c 0x002>;136 dcr-reg = <0x010 0x002>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";53 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x380 0x62>;88 dcr-reg = <0x0a 0x05>;180 dcr-reg = <0xe0 0x9>;214 dcr-reg = <0x12 0x2>;
19 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";55 dcr-reg = <0x0c0 0x009>;70 dcr-reg = <0x010 0x002>;75 dcr-reg = <0x180 0x062>;92 dcr-reg = <0x0a0 0x005>;154 dcr-reg = <0x012 0x002>;
21 dcr-parent = <&{/cpus/cpu@0}>;46 dcr-controller;47 dcr-access-method = "native";60 dcr-reg = <0x0c0 0x009>;70 dcr-reg = <0x0d0 0x009>;80 dcr-reg = <0x00e 0x002>;85 dcr-reg = <0x00c 0x002>;97 dcr-reg = <0x010 0x002>;102 dcr-reg = <0x100 0x027>;107 dcr-reg = <0x180 0x062>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;40 dcr-controller;41 dcr-access-method = "native";54 dcr-reg = <0x0c0 0x009>;64 dcr-reg = <0x0d0 0x009>;76 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x010 0x002>;101 dcr-reg = <0x180 0x062>;124 dcr-reg = <0x0a0 0x005>;129 dcr-reg = <0x012 0x002>;[all …]
47 dcr-controller;48 dcr-access-method = "native";61 dcr-reg = <0x0c0 9>;71 dcr-reg = <0x0d0 9>;81 dcr-reg = <0x00e 2>;86 dcr-reg = <0x00c 2>;98 dcr-reg = <0x010 2>;103 dcr-reg = <0x100 0x027>;108 dcr-reg = <0x180 0x062>;138 dcr-reg = <0x012 2>;
22 dcr-parent = <&{/cpus/cpu@0}>;47 dcr-controller;48 dcr-access-method = "native";61 dcr-reg = <0x0c0 0x009>;71 dcr-reg = <0x0d0 0x009>;83 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x00e 0x002>;98 dcr-reg = <0x00c 0x002>;110 dcr-reg = <0x010 0x002>;115 dcr-reg = <0x100 0x027>;[all …]
19 dcr-parent = <&{/cpus/cpu@0}>;44 dcr-controller;45 dcr-access-method = "native";58 dcr-reg = <0x0c0 0x009>;68 dcr-reg = <0x0d0 0x009>;78 dcr-reg = <0x00e 0x002>;83 dcr-reg = <0x00c 0x002>;95 dcr-reg = <0x010 0x002>;100 dcr-reg = <0x100 0x027>;105 dcr-reg = <0x180 0x062>;[all …]
19 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";55 dcr-reg = <0x0c0 0x009>;70 dcr-reg = <0x010 0x002>;75 dcr-reg = <0x180 0x062>;92 dcr-reg = <0x0a0 0x005>;153 dcr-reg = <0x012 0x002>;
22 dcr-parent = <&{/cpus/cpu@0}>;45 dcr-controller;46 dcr-access-method = "native";59 dcr-reg = <0x0c0 0x009>;69 dcr-reg = <0x0d0 0x009>;81 dcr-reg = <0x0e0 0x009>;93 dcr-reg = <0x0f0 0x009>;103 dcr-reg = <0x00e 0x002>;108 dcr-reg = <0x00c 0x002>;120 dcr-reg = <0x010 0x002>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";55 dcr-reg = <0x0c0 0x009>;65 dcr-reg = <0x0d0 0x009>;77 dcr-reg = <0x0e0 0x009>;94 dcr-reg = <0x010 0x002>;102 dcr-reg = <0x180 0x062>;125 dcr-reg = <0x0a0 0x005>;130 dcr-reg = <0x012 0x002>;[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;41 dcr-controller;42 dcr-access-method = "native";56 dcr-reg = <0x0c0 0x009>;66 dcr-reg = <0x0d0 0x009>;78 dcr-reg = <0x0e0 0x009>;90 dcr-reg = <0x0f0 0x009>;100 dcr-reg = <0x00e 0x002>;105 dcr-reg = <0x00c 0x002>;110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */[all …]
18 dcr-parent = <&{/cpus/cpu@0}>;43 dcr-controller;44 dcr-access-method = "native";57 dcr-reg = <0x0c0 0x009>;67 dcr-reg = <0x0d0 0x009>;79 dcr-reg = <0x0e0 0x009>;91 dcr-reg = <0x0f0 0x009>;101 dcr-reg = <0x00e 0x002>;106 dcr-reg = <0x00c 0x002>;118 dcr-reg = <0x010 0x002>;[all …]
908 if (!(__debug_regs->dcr & DCR_IBE0)) { in gdbstub_set_breakpoint()910 __debug_regs->dcr |= DCR_IBE0; in gdbstub_set_breakpoint()916 if (!(__debug_regs->dcr & DCR_IBE1)) { in gdbstub_set_breakpoint()918 __debug_regs->dcr |= DCR_IBE1; in gdbstub_set_breakpoint()924 if (!(__debug_regs->dcr & DCR_IBE2)) { in gdbstub_set_breakpoint()926 __debug_regs->dcr |= DCR_IBE2; in gdbstub_set_breakpoint()932 if (!(__debug_regs->dcr & DCR_IBE3)) { in gdbstub_set_breakpoint()934 __debug_regs->dcr |= DCR_IBE3; in gdbstub_set_breakpoint()957 if (!(__debug_regs->dcr & (DCR_DRBE0|DCR_DWBE0))) { in gdbstub_set_breakpoint()961 __debug_regs->dcr |= tmp; in gdbstub_set_breakpoint()[all …]
69 __debug_status.dcr &= ~DCR_SE; in debug_stub()126 __debug_status.dcr = DCR_EBE; in debug_stub_init()
130 run->dcr.dcrn = dcrn; in kvmppc_core_emulate_op()131 run->dcr.data = 0; in kvmppc_core_emulate_op()132 run->dcr.is_write = 0; in kvmppc_core_emulate_op()151 run->dcr.dcrn = dcrn; in kvmppc_core_emulate_op()152 run->dcr.data = vcpu->arch.gpr[rs]; in kvmppc_core_emulate_op()153 run->dcr.is_write = 1; in kvmppc_core_emulate_op()