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/arch/ia64/lib/
Didiv32.S48 setf.sig f8 = in0
55 INT_TO_FP(f8, f8)
59 frcpa.s1 f6, p6 = f8, f9 // y0 = frcpa(b)
61 (p6) fmpy.s1 f8 = f8, f6 // q0 = a*y0
67 (p6) fma.s1 f8 = f6, f8, f8 // q1 = e0*q0 + q0
73 (p6) fma.s1 f6 = f6, f8, f8 // q2 = e1*q1 + q1
Didiv64.S42 setf.sig f8 = in0
46 INT_TO_FP(f8, f8)
49 frcpa.s1 f11, p6 = f8, f9 // y0 = frcpa(b)
51 (p6) fmpy.s1 f7 = f8, f11 // q0 = a*y0
64 (p6) fnma.s1 f7 = f9, f10, f8 // r = -b*q2 + a
67 setf.sig f8 = in0 // f8 = a
75 xma.l f11 = f11, f9, f8 // r = q*(-b) + a
/arch/sparc/lib/
DU1memcpy.S65 #define FREG_FROB(f1, f2, f3, f4, f5, f6, f7, f8, f9) \ argument
72 faligndata %f7, %f8, %f60; \
73 faligndata %f8, %f9, %f62;
236 1: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
250 FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
252 3: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
257 1: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
271 FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
273 3: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
278 1: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20)
[all …]
DU3memcpy.S167 EX_LD(LOAD(ldd, %o1 + 0x020, %f8))
170 faligndata %f6, %f8, %f22
173 faligndata %f8, %f10, %f24
196 EX_LD(LOAD(ldd, %o1 + 0x020, %f8))
202 faligndata %f6, %f8, %f22
205 faligndata %f8, %f10, %f24
221 EX_LD(LOAD(ldd, %o1 + 0x020, %f8))
226 faligndata %f6, %f8, %f22
228 faligndata %f8, %f10, %f24
261 faligndata %f0, %f2, %f8
[all …]
Dcopy_page.S110 ldd [%o1 + 0x020], %f8
115 fmovd %f8, %f24
126 ldd [%o1 + 0x060], %f8
133 fmovd %f8, %f24
149 ldd [%o1 + 0x060], %f8
157 fmovd %f8, %f24
181 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
202 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
DNG2memcpy.S87 faligndata %x4, %x5, %f8; \
111 fmovd %x4, %f8;
117 fmovd %x4, %f8; \
124 fmovd %x4, %f8; \
132 fmovd %x4, %f8; \
280 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16)
291 FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12)
294 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18)
305 FREG_LOAD_6(%g2, f0, f2, f4, f6, f8, f10)
308 FREG_FROB(f0, f2, f4, f6, f8, f10, f16, f18, f20)
[all …]
Dxor.S47 fxor %f8, %f24, %f24
74 fxor %f8, %f24, %f24
120 fxor %f8, %f24, %f56
144 fxor %f8, %f24, %f56
188 fxor %f8, %f24, %f24
222 fxor %f8, %f24, %f24
276 fxor %f8, %f24, %f56
320 fxor %f8, %f24, %f56
Dclear_page.S82 faddd %f0, %f2, %f8
/arch/mips/include/asm/
Dfpregdef.h35 #define ft2 $f8
76 #define ft4 $f8
Dasmmacro-32.h21 sdc1 $f8, THREAD_FPR8(\thread)
46 swc1 $f8, THREAD_FPR8(\thread)
79 ldc1 $f8, THREAD_FPR8(\thread)
104 lwc1 $f8, THREAD_FPR8(\thread)
Dasmmacro-64.h22 sdc1 $f8, THREAD_FPR8(\thread)
70 ldc1 $f8, THREAD_FPR8(\thread)
/arch/mips/kernel/
Dr6000_fpu.S34 sdc1 $f8,(SC_FPREGS+64)(a0)
71 ldc1 $f8,(SC_FPREGS+64)(a0)
Dr4k_fpu.S63 EX sdc1 $f8, SC_FPREGS+64(a0)
89 EX sdc1 $f8, SC32_FPREGS+64(a0)
139 EX ldc1 $f8, SC_FPREGS+64(a0)
164 EX ldc1 $f8, SC32_FPREGS+64(a0)
Dr2300_fpu.S41 EX(swc1 $f8,(SC_FPREGS+64)(a0))
93 EX(lwc1 $f8,(SC_FPREGS+64)(a0))
Dr4k_switch.S211 mtc1 t1, $f8
241 dmtc1 t1, $f8
Dr2300_switch.S148 mtc1 t0, $f8
/arch/ia64/kernel/
Dfsys.S304 setf.sig f8 = r10
309 xmpy.l f8 = f8,f7 // nsec_per_cyc*(counter-last_counter)
311 getf.sig r2 = f8
332 (p14) setf.sig f8 = r20
342 (p14) xmpy.hu f8 = f8, f7 // xmpy has 5 cycles latency so use it
344 (p14) getf.sig r2 = f8
Dgate.S230 stf.spill [base0]=f8,32
258 ldf.fill f8=[base0],32
Dhead.S1057 ldf8 f8=[r8]
1061 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1062 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1076 ldf8 f8=[r8]
1080 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1081 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
Dprocess.c131 regs->f8.u.bits[1], regs->f8.u.bits[0], in show_regs()
Dminstate.h200 stf.spill [r2]=f8,32; \
/arch/sparc/kernel/
Dfpu_traps.S37 faddd %f0, %f2, %f8
87 faddd %f0, %f2, %f8
257 fitod %f8, %f62
300 fdtos %f62, %f8
/arch/ia64/include/asm/
Dptrace.h170 struct ia64_fpreg f8; /* scratch */ member
Dkvm_host.h551 struct ia64_fpreg f8; /* scratch */ member
/arch/ia64/kvm/
Dasm-offsets.c168 offsetof(struct kvm_pt_regs, f8)); in foo()

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