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/arch/blackfin/kernel/cplb-nompu/
Dcplbinit.c46 int i_d, i_i; in generate_cplb_tables_cpu() local
54 i_d = i_i = 0; in generate_cplb_tables_cpu()
60 i_tbl[i_i].addr = 0; in generate_cplb_tables_cpu()
61 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB; in generate_cplb_tables_cpu()
70 i_tbl[i_i].addr = addr; in generate_cplb_tables_cpu()
71 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()
79 i_tbl[i_i].addr = L1_CODE_START; in generate_cplb_tables_cpu()
80 i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()
83 first_switched_icplb = i_i; in generate_cplb_tables_cpu()
90 while (i_i < MAX_CPLBS) in generate_cplb_tables_cpu()
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/arch/blackfin/kernel/cplb-mpu/
Dcplbinit.c42 int i_d, i_i; in generate_cplb_tables_cpu() local
60 i_d = i_i = 0; in generate_cplb_tables_cpu()
66 icplb_tbl[cpu][i_i].addr = 0; in generate_cplb_tables_cpu()
67 icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_1KB; in generate_cplb_tables_cpu()
77 icplb_tbl[cpu][i_i].addr = addr; in generate_cplb_tables_cpu()
78 icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0); in generate_cplb_tables_cpu()
87 icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu); in generate_cplb_tables_cpu()
88 icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; in generate_cplb_tables_cpu()
95 icplb_tbl[cpu][i_i].addr = L2_START; in generate_cplb_tables_cpu()
96 icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; in generate_cplb_tables_cpu()
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