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/arch/sh/kernel/
Dtraps_32.c179 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
187 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
190 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
193 count = 1<<(instruction&3); in handle_unaligned_ins()
196 switch (instruction>>12) { in handle_unaligned_ins()
198 if (instruction & 8) { in handle_unaligned_ins()
230 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
238 if (instruction & 4) in handle_unaligned_ins()
252 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
263 if (instruction & 4) in handle_unaligned_ins()
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Dio_trapped.c257 opcode_t instruction; in handle_trapped_io() local
267 if (copy_from_user(&instruction, (void *)(regs->pc), in handle_trapped_io()
268 sizeof(instruction))) { in handle_trapped_io()
273 tmp = handle_unaligned_access(instruction, regs, &trapped_io_access); in handle_trapped_io()
/arch/arm/nwfpe/
Dentry.S88 beq next @ get the next instruction;
91 bl EmulateAll @ emulate the instruction
96 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
113 @ plain LDR instruction. Weird, but it seems harmless.
Dfpmodule.inl24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
/arch/m68k/fpsp040/
Dsmovecr.S5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
Dbugfix.S247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
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/arch/frv/kernel/
Dcmode.S88 # (4) Preload a series of following instructions to the instruction
111 # (5) Flush the content of all caches by the DCEF instruction.
123 # (8) Execute memory barrier instruction (MEMBAR).
132 # (10) Execute memory barrier instruction (MEMBAR).
144 # (13) Execute the instruction just after the memory barrier
145 # instruction that executes the self-loop 256 times. (Meanwhile,
/arch/powerpc/xmon/
Dppc.h179 (unsigned long instruction, long op, int dialect, const char **errmsg);
198 long (*extract) (unsigned long instruction, int dialect, int *invalid);
/arch/m68k/ifpsp060/src/
Disp.S1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
[all …]
Dpfpsp.S1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
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/arch/s390/mm/
Dfault.c250 u16 instruction; in signal_return() local
257 rc = __get_user(instruction, (u16 __user *) regs->psw.addr); in signal_return()
266 if (compat && instruction == 0x0a77) in signal_return()
268 else if (compat && instruction == 0x0aad) in signal_return()
272 if (instruction == 0x0a77) in signal_return()
274 else if (instruction == 0x0aad) in signal_return()
/arch/powerpc/lib/
Dcode-patching.c32 unsigned int instruction; in create_branch() local
44 instruction = 0x48000000 | (flags & 0x3) | (offset & 0x03FFFFFC); in create_branch()
46 return instruction; in create_branch()
52 unsigned int instruction; in create_cond_branch() local
64 instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC); in create_cond_branch()
66 return instruction; in create_cond_branch()
/arch/ia64/scripts/
Dcheck-serialize.S2 .serialize.instruction
/arch/arm/kernel/
Dentry-armv.S194 @ restore SPSR and restart the instruction
248 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ the instruction, or the more conventional lr if we are to treat
259 @ this as a real undefined instruction
261 @ r0 - instruction
276 @ restore SPSR and restart the instruction
297 @ r0 - address of faulting instruction
301 mov r0, r2 @ pass address of aborted instruction.
318 @ restore SPSR and restart the instruction
463 @ it has emulated the instruction, or the more conventional lr
[all …]
/arch/xtensa/kernel/
Dalign.S208 __src_b a4, a4, a5 # a4 has the instruction
287 1: wsr a7, EPC_1 # skip load instruction
330 1: # a7: instruction pointer, a4: instruction, a3: value
335 addi a7, a7, 2 # incr. PC,assume 16-bit instruction
341 addi a7, a7, 1 # increment PC, 32-bit instruction
343 addi a7, a7, 3 # increment PC, 32-bit instruction
367 1: wsr a7, EPC_1 # skip store instruction
/arch/m68k/ifpsp060/
DCHANGES41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
Dilsp.doc35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
Dfskeleton.S111 | instruction.
130 | instruction.
149 | instruction.
168 | instruction.
189 | bit in the FPSR, and does an "rte". The instruction that caused the
227 | frame to the PC of the instruction causing the exception, and does an "rte".
228 | The execution of the instruction then proceeds with an enabled floating-point
245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h48 # Disable instruction prefetching (Octeon Pass1 errata)
53 # Reenable instruction prefetching, not on Pass1
63 # CN30XX Disable instruction prefetching
/arch/arm/mm/
Dabort-lv4t.S31 ldr r8, [r2] @ read arm instruction
76 and r5, r8, #15 << 16 @ Extract 'n' from instruction
94 and r5, r8, #15 << 16 @ Extract 'n' from instruction
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction
120 and r7, r8, #15 @ Extract 'm' from instruction
162 ldrh r8, [r2] @ read instruction
Dabort-ev4t.S26 ldreq r3, [r2] @ read aborted ARM instruction
Dabort-ev4.S24 ldr r3, [r2] @ read aborted ARM instruction
Dabort-ev5t.S26 ldreq r3, [r2] @ read aborted ARM instruction
/arch/mips/dec/prom/
Dlocore.S26 addiu k0, 4 # skip the causing instruction
/arch/powerpc/kernel/
Dalign.c683 unsigned int instr, nb, flags, instruction = 0; in fix_alignment() local
725 instruction = instr; in fix_alignment()
766 if ((instruction & 0xfc00003e) == 0x7c000018) { in fix_alignment()
768 reg |= (instruction & 0x1) << 5; in fix_alignment()
770 if (instruction & 0x200) in fix_alignment()
772 else if (instruction & 0x080) in fix_alignment()
777 if (instruction & 0x100) in fix_alignment()
779 if (instruction & 0x040) in fix_alignment()
782 if ((instruction & 0x400) == 0){ in fix_alignment()

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