Searched refs:io_p2v (Results 1 – 25 of 61) sorted by relevance
123
| /arch/arm/mach-lh7a40x/include/mach/ |
| D | hardware.h | 18 #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) macro
23 # define __REG(x) io_p2v(x)
29 # define __REG(x) (*((volatile u32 *)io_p2v(x)))
40 # define __REG(x) __REGP(io_p2v(x))
43 # define __REG16(x) __REGP16(io_p2v(x))
46 # define __REG8(x) __REGP8(io_p2v(x))
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| D | entry-macro.S | 42 mov \base, #io_p2v(0x80000000) @ APB registers
70 mov \base, #io_p2v(0x80000000) @ APB registers
97 mov \base, #io_p2v(0x80000000) @ APB registers
122 mov \base, #io_p2v(0x80000000) @ APB registers
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| /arch/arm/mach-ns9xxx/include/mach/ |
| D | regs-board-a9m9750dev.h | 16 #define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
17 #define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
18 #define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
19 #define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
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| D | hardware.h | 21 #define io_p2v(x) (0xf0000000 \ macro
36 # define __REG(x) ((void __iomem __force *)io_p2v((x)))
37 # define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
72 # define __REG(x) io_p2v(x)
73 # define __REG2(x, y) io_p2v((x) + 4 * (y))
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| D | debug-macro.S | 18 ldrne \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
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| /arch/arm/mach-aaec2000/include/mach/ |
| D | hardware.h | 30 #define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE ) macro
38 #define __REG(x) (*((volatile u32 *)io_p2v(x)))
43 #define __REG(x) io_p2v(x)
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| D | debug-macro.S | 17 movne \rx, #io_p2v(0x80000000) @ virtual
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| /arch/arm/mach-sa1100/include/mach/ |
| D | hardware.h | 34 #define io_p2v( x ) \ macro
59 # define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
68 # define __REG(x) io_p2v(x)
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| /arch/arm/mach-ns9xxx/ |
| D | processor-ns9360.c | 39 .virtual = io_p2v(0x90000000),
44 .virtual = io_p2v(0xa0100000),
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| /arch/arm/mach-pxa/include/mach/ |
| D | hardware.h | 42 #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) macro
47 # define __REG(x) (*((volatile u32 *)io_p2v(x)))
58 # define __REG(x) io_p2v(x)
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| D | debug-macro.S | 20 movne \rx, #io_p2v(0x40000000) @ virtual
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| D | entry-macro.S | 29 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
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| /arch/arm/mach-netx/ |
| D | xc.c | 108 writel(val, (void __iomem *)io_p2v(adr)); in xc_patch()
161 memcpy((void *)io_p2v(dst), src, size); in xc_request_firmware()
205 x->xpec_base = (void * __iomem)io_p2v(NETX_PA_XPEC(xcno)); in request_xc()
206 x->xmac_base = (void * __iomem)io_p2v(NETX_PA_XMAC(xcno)); in request_xc()
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| D | nxdkn.c | 97 .io_pg_offst = (io_p2v(0x00100000) >> 18) & 0xfffc,
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| /arch/arm/mach-netx/include/mach/ |
| D | hardware.h | 36 #define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT) macro
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| D | entry-macro.S | 33 mov \base, #io_p2v(0x00100000)
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| D | debug-macro.S | 20 movne \rx, #io_p2v(0x00100000) @ virtual
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| /arch/arm/mach-pxa/ |
| D | ezx.c | 673 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
705 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
737 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
764 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
796 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
828 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| D | e350.c | 70 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| D | e330.c | 69 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| D | gpio.c | 28 #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
29 #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
30 #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
31 #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
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| D | mp900.c | 94 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| D | colibri.c | 131 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| D | e400.c | 146 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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| /arch/arm/mach-lh7a40x/ |
| D | arch-kev7a400.c | 115 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
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