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1 /*
2  * arch/arm/mach-ixp4xx/common-pci.c
3  *
4  * IXP4XX PCI routines for all platforms
5  *
6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright (C) 2002 Intel Corporation.
9  * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  */
17 
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/interrupt.h>
22 #include <linux/mm.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/io.h>
29 #include <asm/dma-mapping.h>
30 
31 #include <asm/cputype.h>
32 #include <asm/irq.h>
33 #include <asm/sizes.h>
34 #include <asm/system.h>
35 #include <asm/mach/pci.h>
36 #include <mach/hardware.h>
37 
38 
39 /*
40  * IXP4xx PCI read function is dependent on whether we are
41  * running A0 or B0 (AppleGate) silicon.
42  */
43 int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
44 
45 /*
46  * Base address for PCI regsiter region
47  */
48 unsigned long ixp4xx_pci_reg_base = 0;
49 
50 /*
51  * PCI cfg an I/O routines are done by programming a
52  * command/byte enable register, and then read/writing
53  * the data from a data regsiter. We need to ensure
54  * these transactions are atomic or we will end up
55  * with corrupt data on the bus or in a driver.
56  */
57 static DEFINE_SPINLOCK(ixp4xx_pci_lock);
58 
59 /*
60  * Read from PCI config space
61  */
crp_read(u32 ad_cbe,u32 * data)62 static void crp_read(u32 ad_cbe, u32 *data)
63 {
64 	unsigned long flags;
65 	spin_lock_irqsave(&ixp4xx_pci_lock, flags);
66 	*PCI_CRP_AD_CBE = ad_cbe;
67 	*data = *PCI_CRP_RDATA;
68 	spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
69 }
70 
71 /*
72  * Write to PCI config space
73  */
crp_write(u32 ad_cbe,u32 data)74 static void crp_write(u32 ad_cbe, u32 data)
75 {
76 	unsigned long flags;
77 	spin_lock_irqsave(&ixp4xx_pci_lock, flags);
78 	*PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
79 	*PCI_CRP_WDATA = data;
80 	spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
81 }
82 
check_master_abort(void)83 static inline int check_master_abort(void)
84 {
85 	/* check Master Abort bit after access */
86 	unsigned long isr = *PCI_ISR;
87 
88 	if (isr & PCI_ISR_PFE) {
89 		/* make sure the Master Abort bit is reset */
90 		*PCI_ISR = PCI_ISR_PFE;
91 		pr_debug("%s failed\n", __func__);
92 		return 1;
93 	}
94 
95 	return 0;
96 }
97 
ixp4xx_pci_read_errata(u32 addr,u32 cmd,u32 * data)98 int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
99 {
100 	unsigned long flags;
101 	int retval = 0;
102 	int i;
103 
104 	spin_lock_irqsave(&ixp4xx_pci_lock, flags);
105 
106 	*PCI_NP_AD = addr;
107 
108 	/*
109 	 * PCI workaround  - only works if NP PCI space reads have
110 	 * no side effects!!! Read 8 times. last one will be good.
111 	 */
112 	for (i = 0; i < 8; i++) {
113 		*PCI_NP_CBE = cmd;
114 		*data = *PCI_NP_RDATA;
115 		*data = *PCI_NP_RDATA;
116 	}
117 
118 	if(check_master_abort())
119 		retval = 1;
120 
121 	spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
122 	return retval;
123 }
124 
ixp4xx_pci_read_no_errata(u32 addr,u32 cmd,u32 * data)125 int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
126 {
127 	unsigned long flags;
128 	int retval = 0;
129 
130 	spin_lock_irqsave(&ixp4xx_pci_lock, flags);
131 
132 	*PCI_NP_AD = addr;
133 
134 	/* set up and execute the read */
135 	*PCI_NP_CBE = cmd;
136 
137 	/* the result of the read is now in NP_RDATA */
138 	*data = *PCI_NP_RDATA;
139 
140 	if(check_master_abort())
141 		retval = 1;
142 
143 	spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
144 	return retval;
145 }
146 
ixp4xx_pci_write(u32 addr,u32 cmd,u32 data)147 int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
148 {
149 	unsigned long flags;
150 	int retval = 0;
151 
152 	spin_lock_irqsave(&ixp4xx_pci_lock, flags);
153 
154 	*PCI_NP_AD = addr;
155 
156 	/* set up the write */
157 	*PCI_NP_CBE = cmd;
158 
159 	/* execute the write by writing to NP_WDATA */
160 	*PCI_NP_WDATA = data;
161 
162 	if(check_master_abort())
163 		retval = 1;
164 
165 	spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
166 	return retval;
167 }
168 
ixp4xx_config_addr(u8 bus_num,u16 devfn,int where)169 static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
170 {
171 	u32 addr;
172 	if (!bus_num) {
173 		/* type 0 */
174 		addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
175 		    (where & ~3);
176 	} else {
177 		/* type 1 */
178 		addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
179 			((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
180 	}
181 	return addr;
182 }
183 
184 /*
185  * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
186  * 0 and 3 are not valid indexes...
187  */
188 static u32 bytemask[] = {
189 	/*0*/	0,
190 	/*1*/	0xff,
191 	/*2*/	0xffff,
192 	/*3*/	0,
193 	/*4*/	0xffffffff,
194 };
195 
local_byte_lane_enable_bits(u32 n,int size)196 static u32 local_byte_lane_enable_bits(u32 n, int size)
197 {
198 	if (size == 1)
199 		return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
200 	if (size == 2)
201 		return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
202 	if (size == 4)
203 		return 0;
204 	return 0xffffffff;
205 }
206 
local_read_config(int where,int size,u32 * value)207 static int local_read_config(int where, int size, u32 *value)
208 {
209 	u32 n, data;
210 	pr_debug("local_read_config from %d size %d\n", where, size);
211 	n = where % 4;
212 	crp_read(where & ~3, &data);
213 	*value = (data >> (8*n)) & bytemask[size];
214 	pr_debug("local_read_config read %#x\n", *value);
215 	return PCIBIOS_SUCCESSFUL;
216 }
217 
local_write_config(int where,int size,u32 value)218 static int local_write_config(int where, int size, u32 value)
219 {
220 	u32 n, byte_enables, data;
221 	pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
222 	n = where % 4;
223 	byte_enables = local_byte_lane_enable_bits(n, size);
224 	if (byte_enables == 0xffffffff)
225 		return PCIBIOS_BAD_REGISTER_NUMBER;
226 	data = value << (8*n);
227 	crp_write((where & ~3) | byte_enables, data);
228 	return PCIBIOS_SUCCESSFUL;
229 }
230 
byte_lane_enable_bits(u32 n,int size)231 static u32 byte_lane_enable_bits(u32 n, int size)
232 {
233 	if (size == 1)
234 		return (0xf & ~BIT(n)) << 4;
235 	if (size == 2)
236 		return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
237 	if (size == 4)
238 		return 0;
239 	return 0xffffffff;
240 }
241 
ixp4xx_pci_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)242 static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
243 {
244 	u32 n, byte_enables, addr, data;
245 	u8 bus_num = bus->number;
246 
247 	pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
248 		bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
249 
250 	*value = 0xffffffff;
251 	n = where % 4;
252 	byte_enables = byte_lane_enable_bits(n, size);
253 	if (byte_enables == 0xffffffff)
254 		return PCIBIOS_BAD_REGISTER_NUMBER;
255 
256 	addr = ixp4xx_config_addr(bus_num, devfn, where);
257 	if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
258 		return PCIBIOS_DEVICE_NOT_FOUND;
259 
260 	*value = (data >> (8*n)) & bytemask[size];
261 	pr_debug("read_config_byte read %#x\n", *value);
262 	return PCIBIOS_SUCCESSFUL;
263 }
264 
ixp4xx_pci_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)265 static int ixp4xx_pci_write_config(struct pci_bus *bus,  unsigned int devfn, int where, int size, u32 value)
266 {
267 	u32 n, byte_enables, addr, data;
268 	u8 bus_num = bus->number;
269 
270 	pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
271 		size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
272 
273 	n = where % 4;
274 	byte_enables = byte_lane_enable_bits(n, size);
275 	if (byte_enables == 0xffffffff)
276 		return PCIBIOS_BAD_REGISTER_NUMBER;
277 
278 	addr = ixp4xx_config_addr(bus_num, devfn, where);
279 	data = value << (8*n);
280 	if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
281 		return PCIBIOS_DEVICE_NOT_FOUND;
282 
283 	return PCIBIOS_SUCCESSFUL;
284 }
285 
286 struct pci_ops ixp4xx_ops = {
287 	.read =  ixp4xx_pci_read_config,
288 	.write = ixp4xx_pci_write_config,
289 };
290 
291 /*
292  * PCI abort handler
293  */
abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)294 static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
295 {
296 	u32 isr, status;
297 
298 	isr = *PCI_ISR;
299 	local_read_config(PCI_STATUS, 2, &status);
300 	pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
301 		"status = %#x\n", addr, isr, status);
302 
303 	/* make sure the Master Abort bit is reset */
304 	*PCI_ISR = PCI_ISR_PFE;
305 	status |= PCI_STATUS_REC_MASTER_ABORT;
306 	local_write_config(PCI_STATUS, 2, status);
307 
308 	/*
309 	 * If it was an imprecise abort, then we need to correct the
310 	 * return address to be _after_ the instruction.
311 	 */
312 	if (fsr & (1 << 10))
313 		regs->ARM_pc += 4;
314 
315 	return 0;
316 }
317 
318 
319 /*
320  * Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
321  */
ixp4xx_pci_platform_notify(struct device * dev)322 static int ixp4xx_pci_platform_notify(struct device *dev)
323 {
324 	if(dev->bus == &pci_bus_type) {
325 		*dev->dma_mask =  SZ_64M - 1;
326 		dev->coherent_dma_mask = SZ_64M - 1;
327 		dmabounce_register_dev(dev, 2048, 4096);
328 	}
329 	return 0;
330 }
331 
ixp4xx_pci_platform_notify_remove(struct device * dev)332 static int ixp4xx_pci_platform_notify_remove(struct device *dev)
333 {
334 	if(dev->bus == &pci_bus_type) {
335 		dmabounce_unregister_dev(dev);
336 	}
337 	return 0;
338 }
339 
dma_needs_bounce(struct device * dev,dma_addr_t dma_addr,size_t size)340 int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
341 {
342 	return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
343 }
344 
345 /*
346  * Only first 64MB of memory can be accessed via PCI.
347  * We use GFP_DMA to allocate safe buffers to do map/unmap.
348  * This is really ugly and we need a better way of specifying
349  * DMA-capable regions of memory.
350  */
ixp4xx_adjust_zones(int node,unsigned long * zone_size,unsigned long * zhole_size)351 void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
352 	unsigned long *zhole_size)
353 {
354 	unsigned int sz = SZ_64M >> PAGE_SHIFT;
355 
356 	/*
357 	 * Only adjust if > 64M on current system
358 	 */
359 	if (node || (zone_size[0] <= sz))
360 		return;
361 
362 	zone_size[1] = zone_size[0] - sz;
363 	zone_size[0] = sz;
364 	zhole_size[1] = zhole_size[0];
365 	zhole_size[0] = 0;
366 }
367 
ixp4xx_pci_preinit(void)368 void __init ixp4xx_pci_preinit(void)
369 {
370 	unsigned long cpuid = read_cpuid_id();
371 
372 	/*
373 	 * Determine which PCI read method to use.
374 	 * Rev 0 IXP425 requires workaround.
375 	 */
376 	if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
377 		printk("PCI: IXP42x A0 silicon detected - "
378 			"PCI Non-Prefetch Workaround Enabled\n");
379 		ixp4xx_pci_read = ixp4xx_pci_read_errata;
380 	} else
381 		ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
382 
383 
384 	/* hook in our fault handler for PCI errors */
385 	hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
386 
387 	pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
388 
389 	/*
390 	 * We use identity AHB->PCI address translation
391 	 * in the 0x48000000 to 0x4bffffff address space
392 	 */
393 	*PCI_PCIMEMBASE = 0x48494A4B;
394 
395 	/*
396 	 * We also use identity PCI->AHB address translation
397 	 * in 4 16MB BARs that begin at the physical memory start
398 	 */
399 	*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
400 		((PHYS_OFFSET & 0xFF000000) >> 8) +
401 		((PHYS_OFFSET & 0xFF000000) >> 16) +
402 		((PHYS_OFFSET & 0xFF000000) >> 24) +
403 		0x00010203;
404 
405 	if (*PCI_CSR & PCI_CSR_HOST) {
406 		printk("PCI: IXP4xx is host\n");
407 
408 		pr_debug("setup BARs in controller\n");
409 
410 		/*
411 		 * We configure the PCI inbound memory windows to be
412 		 * 1:1 mapped to SDRAM
413 		 */
414 		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
415 		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
416 		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
417 		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
418 
419 		/*
420 		 * Enable CSR window at 0xff000000.
421 		 */
422 		local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
423 
424 		/*
425 		 * Enable the IO window to be way up high, at 0xfffffc00
426 		 */
427 		local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
428 	} else {
429 		printk("PCI: IXP4xx is target - No bus scan performed\n");
430 	}
431 
432 	printk("PCI: IXP4xx Using %s access for memory space\n",
433 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
434 			"direct"
435 #else
436 			"indirect"
437 #endif
438 		);
439 
440 	pr_debug("clear error bits in ISR\n");
441 	*PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
442 
443 	/*
444 	 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
445 	 * respond to PCI configuration cycles. Specify that the AHB bus is
446 	 * operating in big endian mode. Set up byte lane swapping between
447 	 * little-endian PCI and the big-endian AHB bus
448 	 */
449 #ifdef __ARMEB__
450 	*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
451 #else
452 	*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
453 #endif
454 
455 	pr_debug("DONE\n");
456 }
457 
ixp4xx_setup(int nr,struct pci_sys_data * sys)458 int ixp4xx_setup(int nr, struct pci_sys_data *sys)
459 {
460 	struct resource *res;
461 
462 	if (nr >= 1)
463 		return 0;
464 
465 	res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
466 	if (res == NULL) {
467 		/*
468 		 * If we're out of memory this early, something is wrong,
469 		 * so we might as well catch it here.
470 		 */
471 		panic("PCI: unable to allocate resources?\n");
472 	}
473 
474 	local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
475 
476 	res[0].name = "PCI I/O Space";
477 	res[0].start = 0x00000000;
478 	res[0].end = 0x0000ffff;
479 	res[0].flags = IORESOURCE_IO;
480 
481 	res[1].name = "PCI Memory Space";
482 	res[1].start = PCIBIOS_MIN_MEM;
483 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
484 	res[1].end = 0x4bffffff;
485 #else
486 	res[1].end = 0x4fffffff;
487 #endif
488 	res[1].flags = IORESOURCE_MEM;
489 
490 	request_resource(&ioport_resource, &res[0]);
491 	request_resource(&iomem_resource, &res[1]);
492 
493 	sys->resource[0] = &res[0];
494 	sys->resource[1] = &res[1];
495 	sys->resource[2] = NULL;
496 
497 	platform_notify = ixp4xx_pci_platform_notify;
498 	platform_notify_remove = ixp4xx_pci_platform_notify_remove;
499 
500 	return 1;
501 }
502 
ixp4xx_scan_bus(int nr,struct pci_sys_data * sys)503 struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
504 {
505 	return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
506 }
507 
508 /*
509  * We override these so we properly do dmabounce otherwise drivers
510  * are able to set the dma_mask to 0xffffffff and we can no longer
511  * trap bounces. :(
512  *
513  * We just return true on everyhing except for < 64MB in which case
514  * we will fail miseralby and die since we can't handle that case.
515  */
516 int
pci_set_dma_mask(struct pci_dev * dev,u64 mask)517 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
518 {
519 	if (mask >= SZ_64M - 1 )
520 		return 0;
521 
522 	return -EIO;
523 }
524 
525 int
pci_set_consistent_dma_mask(struct pci_dev * dev,u64 mask)526 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
527 {
528 	if (mask >= SZ_64M - 1 )
529 		return 0;
530 
531 	return -EIO;
532 }
533 
534 EXPORT_SYMBOL(ixp4xx_pci_read);
535 EXPORT_SYMBOL(ixp4xx_pci_write);
536 
537