Searched refs:latency (Results 1 – 18 of 18) sorted by relevance
/arch/sh/lib/ |
D | memcpy-sh4.S | 30 mov r4,r2 ! 5 MT (0 cycles latency) 32 mov.l @(r0,r5),r7 ! 21 LS (2 cycles latency) 39 3: mov.l @(r0,r5),r1 ! 21 LS (latency=2) ! NMLK 40 mov r7, r3 ! 5 MT (latency=0) ! RQPO 45 mov r1,r6 ! 5 MT (latency=0) 49 mov r1, r7 ! 5 MT (latency=0) 56 3: mov.l @(r0,r5),r1 ! 21 LS (latency=2) ! KLMN 57 mov r7,r3 ! 5 MT (latency=0) ! OPQR 63 mov r1,r6 ! 5 MT (latency=0) 66 mov r1,r7 ! 5 MT (latency=0) [all …]
|
/arch/cris/arch-v10/lib/ |
D | dram_init.S | 49 ; CAS latency = 2 && bus_width = 32 => 0x40 50 ; CAS latency = 3 && bus_width = 32 => 0x60 51 ; CAS latency = 2 && bus_width = 16 => 0x20 52 ; CAS latency = 3 && bus_width = 16 => 0x30 60 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2 63 and.d 0x03, $r1 ; Get CAS latency 68 cmp.d 0x00, $r1 ; CAS latency = 2? 71 or.d 0x20, $r2 ; CAS latency = 3 75 cmp.d 0x01, $r1 ; CAS latency = 2? 78 or.d 0x20, $r2 ; CAS latency = 3
|
/arch/x86/kernel/cpu/cpufreq/ |
D | powernow-k7.c | 101 static unsigned int latency; variable 219 fidvidctl.bits.SGTC = latency; in change_FID() 234 fidvidctl.bits.SGTC = latency; in change_VID() 401 if (latency < pc.bits.sgtc) in powernow_acpi_init() 402 latency = pc.bits.sgtc; in powernow_acpi_init() 469 latency = psb->settlingtime; in powernow_decode_bios() 470 if (latency < 100) { in powernow_decode_bios() 472 "Should be at least 100. Correcting.\n", latency); in powernow_decode_bios() 473 latency = 100; in powernow_decode_bios() 553 sgtc = 100 * m * latency; in fixup_sgtc() [all …]
|
D | longhaul.c | 894 if (cx->address > 0 && cx->latency <= 1000) in longhaul_cpu_init()
|
/arch/cris/arch-v32/mach-fs/ |
D | dram_init.S | 36 ; CAS latency = 2 && bus_width = 32 => 0x40 37 ; CAS latency = 3 && bus_width = 32 => 0x60 38 ; CAS latency = 2 && bus_width = 16 => 0x20 39 ; CAS latency = 3 && bus_width = 16 => 0x30 46 move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2 48 and.d 0x07, $r1 ; Get CAS latency
|
/arch/blackfin/ |
D | Kconfig | 694 into L1 instruction memory. (less latency) 702 (less latency) 709 into L1 instruction memory. (less latency) 716 into L1 instruction memory. (less latency) 723 into L1 instruction memory. (less latency) 730 into L1 instruction memory. (less latency) 737 into L1 instruction memory. (less latency) 744 into L1 instruction memory. (less latency) 751 into L1 instruction memory. (less latency) 758 into L1 instruction memory. (less latency) [all …]
|
/arch/alpha/lib/ |
D | ev67-strrchr.S | 100 nop # E : hide the cmov latency (2) behind ctlz latency
|
D | ev67-strchr.S | 83 cmoveq t1, $31, v0 # E : Two mapping slots, latency = 2
|
/arch/alpha/include/asm/ |
D | core_irongate.h | 40 igcsr32 latency; /* 0x0C - header type, PCI latency */ member
|
/arch/cris/arch-v32/mach-a3/ |
D | dram_init.S | 64 ; Set latency
|
/arch/cris/arch-v32/lib/ |
D | checksumcopy.S | 31 addoq -10*4, $acr, $acr ; loop counter in latency cycle
|
/arch/sparc/mm/ |
D | init_64.c | 879 u64 latency; member 1027 m->latency = *val; in grab_mlgroups() 1035 count - 1, m->node, m->latency, m->match, m->mask); in grab_mlgroups() 1124 if (m->latency < best_latency) { in numa_attach_mlgroup() 1126 best_latency = m->latency; in numa_attach_mlgroup() 1145 index, n->mask, n->val, candidate->latency); in numa_attach_mlgroup()
|
/arch/sh/kernel/cpu/sh5/ |
D | switchto.S | 106 ! do this early as pta->gettr has no pipeline forwarding (=> 5 cycle latency)
|
/arch/xtensa/ |
D | Kconfig | 91 This option reduces the latency of the kernel when reacting to
|
/arch/mn10300/ |
D | Kconfig | 180 This option reduces the latency of the kernel when reacting to
|
/arch/m32r/ |
D | Kconfig | 284 This option reduces the latency of the kernel when reacting to
|
/arch/cris/arch-v10/drivers/ |
D | Kconfig | 43 Try 0-3 for low latency applications. Approx 5 for high load
|
/arch/arm/ |
D | Kconfig | 854 This option reduces the latency of the kernel when reacting to
|