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Searched refs:membase (Results 1 – 25 of 64) sorted by relevance

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/arch/blackfin/mach-bf548/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
39 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
40 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
41 #define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
43 #define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
44 #define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
46 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
[all …]
/arch/blackfin/mach-bf538/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45 #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46 #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
[all …]
/arch/blackfin/mach-bf518/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45 #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46 #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
[all …]
/arch/blackfin/mach-bf561/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
[all …]
/arch/blackfin/mach-bf533/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
[all …]
/arch/blackfin/mach-bf527/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
45 #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
46 #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
[all …]
/arch/blackfin/mach-bf537/include/mach/
Dbfin_serial_5xx.h36 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
37 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
38 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
39 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
40 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
41 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
42 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
44 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
45 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
46 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
[all …]
/arch/mips/cavium-octeon/
Dserial.c29 int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); in octeon_serial_in()
32 cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); in octeon_serial_in()
33 rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); in octeon_serial_in()
46 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); in octeon_serial_out()
108 p->membase = (void *) CVMX_MIO_UARTX_RBR(0); in octeon_serial_init()
117 p->membase = (void *) CVMX_MIO_UARTX_RBR(1); in octeon_serial_init()
125 p->membase = (void *) CVMX_MIO_UART2_RBR; in octeon_serial_init()
/arch/arm/mach-omap2/
Dserial.c30 .membase = IO_ADDRESS(OMAP_UART1_BASE),
38 .membase = IO_ADDRESS(OMAP_UART2_BASE),
46 .membase = IO_ADDRESS(OMAP_UART3_BASE),
62 return (unsigned int)__raw_readb(up->membase + offset); in serial_read_reg()
69 __raw_writeb(value, p->membase + offset); in serial_write_reg()
122 p->membase = NULL; in omap_serial_init()
/arch/arm/mach-davinci/
Dserial.c42 return (unsigned int)__raw_readb(up->membase + offset); in davinci_serial_in()
49 __raw_writeb(value, p->membase + offset); in davinci_serial_outp()
54 .membase = (char *)IO_ADDRESS(DAVINCI_UART0_BASE),
/arch/arm/mach-omap1/
Dserial.c41 return (unsigned int)__raw_readb(up->membase + offset); in omap_serial_in()
48 __raw_writeb(value, p->membase + offset); in omap_serial_outp()
70 .membase = IO_ADDRESS(OMAP_UART1_BASE),
79 .membase = IO_ADDRESS(OMAP_UART2_BASE),
88 .membase = IO_ADDRESS(OMAP_UART3_BASE),
138 serial_platform_data[i].membase = NULL; in omap_serial_init()
/arch/arm/mach-h720x/
Dcpu-h7202.c51 .membase = (void*)SERIAL0_VIRT,
60 .membase = (void*)SERIAL1_VIRT,
70 .membase = (void*)SERIAL2_VIRT,
79 .membase = (void*)SERIAL3_VIRT,
/arch/arm/kernel/
Disa.c69 register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) in register_isa_ports() argument
71 isa_membase = membase; in register_isa_ports()
/arch/arm/mach-iop33x/
Duart.c35 .membase = (char *)IOP33X_UART0_VIRT,
85 .membase = (char *)IOP33X_UART1_VIRT,
/arch/mips/emma/markeins/
Dplatform.c112 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
119 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
126 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
/arch/mips/pmc-sierra/msp71xx/
Dmsp_serial.c58 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); in msp_serial_setup()
87 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); in msp_serial_setup()
/arch/mips/nxp/pnx8550/common/
Dplatform.c70 .membase = (void __iomem *)PNX8550_UART_PORT0,
83 .membase = (void __iomem *)PNX8550_UART_PORT1,
/arch/arm/mach-ixp4xx/
Dcoyote-setup.c56 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
92 coyote_uart_data[0].membase = in coyote_init()
Davila-setup.c80 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
89 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Ddsmg600-setup.c111 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
120 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dnslu2-setup.c126 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
135 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dnas100d-setup.c119 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
/arch/mips/rb532/
Dserial.c43 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
/arch/arm/mach-mx3/
Dmx31ads.c54 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
/arch/mips/bcm47xx/
Dserial.c38 p->membase = (void *) ssb_port->regs; in uart8250_init()

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