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Searched refs:mmio_base (Results 1 – 10 of 10) sorted by relevance

/arch/arm/mach-pxa/
Dssp.c47 status = __raw_readl(ssp->mmio_base + SSSR); in ssp_interrupt()
48 __raw_writel(status, ssp->mmio_base + SSSR); in ssp_interrupt()
80 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) { in ssp_write_word()
86 __raw_writel(data, ssp->mmio_base + SSDR); in ssp_write_word()
111 while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) { in ssp_read_word()
117 *data = __raw_readl(ssp->mmio_base + SSDR); in ssp_read_word()
136 while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) { in ssp_flush()
145 while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) { in ssp_flush()
148 (void)__raw_readl(ssp->mmio_base + SSDR); in ssp_flush()
152 } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY); in ssp_flush()
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Dpwm.c40 void __iomem *mmio_base; member
80 __raw_writel(prescale, pwm->mmio_base + PWMCR); in pwm_config()
81 __raw_writel(dc, pwm->mmio_base + PWMDCR); in pwm_config()
82 __raw_writel(pv, pwm->mmio_base + PWMPCR); in pwm_config()
189 pwm->mmio_base = parent_pwm->mmio_base + 0x10; in pwm_probe()
208 pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); in pwm_probe()
209 if (pwm->mmio_base == NULL) { in pwm_probe()
266 iounmap(pwm->mmio_base); in pwm_remove()
/arch/arm/mach-pxa/include/mach/
Dssp.h37 void __iomem *mmio_base; member
91 __raw_writel(val, dev->mmio_base + reg); in ssp_write_reg()
102 return __raw_readl(dev->mmio_base + reg); in ssp_read_reg()
/arch/x86/kernel/
Damd_iommu_init.c206 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
210 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
219 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
223 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
232 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
234 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
241 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
243 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
284 if (iommu->mmio_base) in iommu_unmap_mmio_space()
285 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
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Damd_iommu.c200 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
201 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_poll_events()
208 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
238 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in __iommu_queue_command()
242 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in __iommu_queue_command()
245 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in __iommu_queue_command()
283 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in __iommu_wait_for_completion()
289 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); in __iommu_wait_for_completion()
/arch/ia64/pci/
Dpci.c136 u64 mmio_base; in new_space() local
142 mmio_base = (u64) ioremap(phys_base, 0); in new_space()
144 if (io_space[i].mmio_base == mmio_base && in new_space()
155 io_space[i].mmio_base = mmio_base; in new_space()
193 base = __pa(io_space[space_nr].mmio_base); in add_io_space()
/arch/ia64/include/asm/
Dio.h49 unsigned long mmio_base; /* base in MMIO space */ member
140 return (void *) (space->mmio_base | offset); in __ia64_mk_io_addr()
/arch/x86/include/asm/
Damd_iommu_types.h264 u8 *mmio_base; member
/arch/ia64/sn/kernel/
Dsetup.c421 io_space[0].mmio_base = in sn_setup()
/arch/ia64/kernel/
Dsetup.c435 io_space[0].mmio_base = ia64_iobase; in io_port_init()