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Searched refs:mtdcr (Results 1 – 8 of 8) sorted by relevance

/arch/powerpc/sysdev/
Dppc4xx_soc.c37 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr); in l2c_diag()
38 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG); in l2c_diag()
64 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in l2c_error_handler()
65 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); in l2c_error_handler()
129 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC, in ppc4xx_l2c_probe()
131 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR, in ppc4xx_l2c_probe()
133 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR, in ppc4xx_l2c_probe()
135 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR, in ppc4xx_l2c_probe()
137 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR, in ppc4xx_l2c_probe()
144 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); in ppc4xx_l2c_probe()
[all …]
Duic.c70 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
73 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
87 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_irq()
98 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); in uic_ack_irq()
114 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_ack_irq()
124 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
166 mtdcr(uic->dcrbase + UIC_PR, pr); in uic_set_irq_type()
167 mtdcr(uic->dcrbase + UIC_TR, tr); in uic_set_irq_type()
291 mtdcr(uic->dcrbase + UIC_ER, 0); in uic_init_one()
292 mtdcr(uic->dcrbase + UIC_CR, 0); in uic_init_one()
[all …]
Ddcr-low.S38 mtdcr 0,r4; blr
43 mtdcr dcr,r4; blr
/arch/powerpc/boot/
Ddcr.h10 #define mtdcr(rn, val) \ macro
18 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
21 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
22 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
173 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
176 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
177 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
191 mtdcr(DCRN_CPR0_CFGADDR, offset); \
194 mtdcr(DCRN_CPR0_CFGADDR, offset); \
195 mtdcr(DCRN_CPR0_CFGDATA, data); })
D4xx.c266 mtdcr(DCRN_MAL0_CFG, MAL_RESET); in ibm4xx_quiesce_eth()
282 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); in ibm4xx_fixup_ebc_ranges()
579 mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); in ibm405gp_fixup_clocks()
/arch/powerpc/include/asm/
Ddcr-native.h41 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
75 #define mtdcr(rn, v) \ macro
/arch/powerpc/kernel/
Dcpu_setup_44x.S69 mtdcr DCRN_PLB4A0_ACR,r3
/arch/powerpc/kvm/
D44x_emulate.c124 mtdcr(DCRN_CPR0_CONFIG_ADDR, in kvmppc_core_emulate_op()