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Searched refs:queue (Results 1 – 11 of 11) sorted by relevance

/arch/arm/mach-ixp4xx/include/mach/
Dqmgr.h60 void qmgr_set_irq(unsigned int queue, int src,
62 void qmgr_enable_irq(unsigned int queue);
63 void qmgr_disable_irq(unsigned int queue);
70 int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
75 int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
78 #define qmgr_request_queue(queue, len, nearly_empty_watermark, \ argument
80 __qmgr_request_queue(queue, len, nearly_empty_watermark, \
84 void qmgr_release_queue(unsigned int queue);
87 static inline void qmgr_put_entry(unsigned int queue, u32 val) in qmgr_put_entry() argument
91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */ in qmgr_put_entry()
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/arch/arm/mach-ixp4xx/
Dixp4xx_qmgr.c28 void qmgr_set_irq(unsigned int queue, int src, in qmgr_set_irq() argument
31 u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ in qmgr_set_irq()
32 int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ in qmgr_set_irq()
38 irq_handlers[queue] = handler; in qmgr_set_irq()
39 irq_pdevs[queue] = pdev; in qmgr_set_irq()
58 void qmgr_enable_irq(unsigned int queue) in qmgr_enable_irq() argument
63 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), in qmgr_enable_irq()
68 void qmgr_disable_irq(unsigned int queue) in qmgr_disable_irq() argument
73 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), in qmgr_disable_irq()
75 __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */ in qmgr_disable_irq()
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DKconfig199 This driver supports IXP4xx built-in hardware queue manager
/arch/arm/plat-omap/
Dmailbox.c77 struct request_queue *q = mbox->txq->queue; in omap_mbox_msg_send()
101 struct omap_mbox *mbox = mq->queue->queuedata; in mbox_tx_work()
102 struct request_queue *q = mbox->txq->queue; in mbox_tx_work()
132 struct omap_mbox *mbox = mq->queue->queuedata; in mbox_rx_work()
133 struct request_queue *q = mbox->rxq->queue; in mbox_rx_work()
181 struct request_queue *q = mbox->rxq->queue; in __mbox_rx_interrupt()
252 struct request_queue *q = mbox->rxq->queue; in omap_mbox_read()
309 mq->queue = q; in mbox_queue_alloc()
321 blk_cleanup_queue(q->queue); in mbox_queue_free()
/arch/powerpc/sysdev/
Daxonram.c108 axon_ram_make_request(struct request_queue *queue, struct bio *bio) in axon_ram_make_request() argument
244 bank->disk->queue = blk_alloc_queue(GFP_KERNEL); in axon_ram_probe()
245 if (bank->disk->queue == NULL) { in axon_ram_probe()
252 blk_queue_make_request(bank->disk->queue, axon_ram_make_request); in axon_ram_probe()
253 blk_queue_hardsect_size(bank->disk->queue, AXON_RAM_SECTOR_SIZE); in axon_ram_probe()
/arch/ia64/hp/sim/
Dsimscsi.c69 } queue[SIMSCSI_REQ_QUEUE_LEN]; variable
103 while ((sc = queue[rd].sc) != NULL) { in simscsi_interrupt()
105 queue[rd].sc = NULL; in simscsi_interrupt()
322 queue[wr].sc = sc; in simscsi_queuecommand()
/arch/um/drivers/
Dubd_kern.c158 struct request_queue *queue; member
507 do_ubd_request(ubd->queue); in ubd_handler()
771 blk_queue_max_sectors(ubd_dev->queue, 8 * sizeof(long)); in ubd_open_dev()
804 blk_cleanup_queue(ubd_dev->queue); in ubd_device_release()
837 disk->queue = ubd_devs[unit].queue; in ubd_disk_register()
866 ubd_dev->queue = blk_init_queue(do_ubd_request, &ubd_dev->lock); in ubd_add()
867 if (ubd_dev->queue == NULL) { in ubd_add()
871 ubd_dev->queue->queuedata = ubd_dev; in ubd_add()
873 blk_queue_max_hw_segments(ubd_dev->queue, MAX_SG); in ubd_add()
896 blk_cleanup_queue(ubd_dev->queue); in ubd_add()
/arch/arm/plat-omap/include/mach/
Dmailbox.h40 struct request_queue *queue; member
/arch/arm/plat-mxc/include/mach/
Dipu.h169 struct list_head queue; /* queued tx-descriptors */ member
/arch/arm/mach-pxa/
Dsleep.S361 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
/arch/x86/math-emu/
DREADME135 queue of the CPU before the mov instruction is executed. If the
137 in the prefetch queue and memory will be inconsistent when the FPU