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Searched refs:r16 (Results 1 – 25 of 72) sorted by relevance

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/arch/ia64/kvm/
Dtrampoline.S19 mov r16 = b0; \
22 st8 [r2]=r16,16; \
25 mov r16 = b2; \
28 st8 [r2]=r16,16; \
31 mov r16 = b4; \
34 st8 [r2]=r16; \
45 ld8 r16=[r2],16; \
48 mov b0 = r16; \
51 ld8 r16=[r2],16; \
54 mov b2 = r16; \
[all …]
Dkvm_minstate.h101 KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
111 mov r1 = r16; \
120 adds r16 = PT(CR_IPSR),r1; \
123 st8 [r16] = r29; /* save cr.ipsr */ \
129 adds r16 = PT(R8),r1; /* initialize first base pointer */\
132 .mem.offset 0,0; st8.spill [r16] = r8,16; \
135 .mem.offset 0,0; st8.spill [r16] = r10,24; \
141 st8 [r16] = r9,16; /* save cr.iip */ \
145 st8 [r16] = r25,16; /* save ar.unat */ \
149 st8 [r16] = r27,16; /* save ar.rsc */ \
[all …]
Doptvfault.S27 add r16=VMM_VPD_BASE_OFFSET,r21; \
34 ld8 r16 = [r16]; \
41 mov r25 =r16; \
124 add r16=VMM_VCPU_LAST_ITC_OFFSET,r21
134 st8 [r16] = r19
149 extr.u r16=r25,20,7
154 shladd r16=r16,4,r20
158 mov b0=r16
180 extr.u r16=r25,20,7
185 shladd r16=r16,4,r20
[all …]
Dvmm_ivt.S148 mov r16=cr.ifa // get address that caused the TLB miss
154 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
171 mov r16=cr.ifa // get address that caused the TLB miss
177 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
291 adds r16=PT(CR_IPSR),r1
294 st8 [r16]=r29 /* save cr.ipsr */
299 adds r16=PT(R8),r1 /* initialize first base pointer */
303 .mem.offset 0,0; st8.spill [r16]=r8,16
306 .mem.offset 0,0; st8.spill [r16]=r10,24
309 st8 [r16]=r28,16 /* save cr.iip */
[all …]
/arch/ia64/include/asm/xen/
Dminstate.h28 mov r16=IA64_KR(CURRENT); /* M */ \
37 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
39 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
40 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
41 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
64 adds r16=PT(CR_IPSR),r1; \
67 st8 [r16]=r29; /* save cr.ipsr */ \
74 adds r16=PT(R8),r1; /* initialize first base pointer */ \
78 .mem.offset 0,0; st8.spill [r16]=r8,16; \
81 .mem.offset 0,0; st8.spill [r16]=r10,24; \
[all …]
/arch/ia64/kernel/
Dminstate.h48 mov r16=IA64_KR(CURRENT); /* M */ \
58 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
60 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
61 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
62 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
85 adds r16=PT(CR_IPSR),r1; \
88 st8 [r16]=r29; /* save cr.ipsr */ \
95 adds r16=PT(R8),r1; /* initialize first base pointer */ \
99 .mem.offset 0,0; st8.spill [r16]=r8,16; \
102 .mem.offset 0,0; st8.spill [r16]=r10,24; \
[all …]
Divt.S74 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
113 MOV_FROM_IFA(r16) // get address that caused the TLB miss
122 shl r21=r16,3 // shift bit 60 into sign bit
123 shr.u r17=r16,61 // get the region number into r17
241 (p6) ptc.l r16,r27 // purge translation
259 MOV_FROM_IFA(r16) // get virtual address
286 (p7) ptc.l r16,r20
303 MOV_FROM_IFA(r16) // get virtual address
330 (p7) ptc.l r16,r20
341 MOV_FROM_IFA(r16) // get address that caused the TLB miss
[all …]
Drelocate_kernel.S40 movl r16 = IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_IC
49 mov cr.ipsr=r16
98 movl r16=KERNEL_START
101 ptr.i r16, r18
102 ptr.d r16, r18
108 mov r16=in3
111 ptr.i r16,r18
117 mov r16=IA64_KR(CURRENT_STACK)
119 shl r16=r16,IA64_GRANULE_SHIFT
122 add r16=r19,r16
[all …]
Djprobes.S66 movl r16=invalidate_restore_cfm
68 mov b6=r16
73 mov r16=ar.rsc
79 mov ar.rsc=r16
Dmca_asm.S98 movl r16=KERNEL_START
101 ptr.i r16, r18
102 ptr.d r16, r18
111 ld8 r16=[r2]
114 ptr.i r16,r18
119 mov r16=IA64_KR(CURRENT_STACK)
121 shl r16=r16,IA64_GRANULE_SHIFT
124 add r16=r19,r16
127 ptr.d r16,r18
172 mov r16=IA64_TR_KERNEL
[all …]
Defi_stub.S57 movl r16=PSR_BITS_TO_CLEAR
64 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
77 mov r16=loc3
Desi_stub.S74 movl r16=PSR_BITS_TO_CLEAR
81 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
87 mov r16=loc3 // save virtual mode psr
Dentry.S78 adds r16=PT(CR_IPSR)+16,sp
80 ld8 r16=[r16]
111 tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
128 alloc r16=ar.pfs,8,2,6,0
132 mov loc1=r16 // save ar.pfs across do_fork
160 alloc r16=ar.pfs,8,2,6,0
164 mov loc1=r16 // save ar.pfs across do_fork
192 alloc r16=ar.pfs,1,0,0,0
334 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
408 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
[all …]
Dfsys.S64 add r17=IA64_TASK_GROUP_LEADER_OFFSET,r16
67 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
97 add r17=IA64_TASK_GROUP_LEADER_OFFSET,r16
100 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
144 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
145 add r17=IA64_TASK_TGIDLINK_OFFSET,r16
153 add r18=IA64_TASK_CLEAR_CHILD_TID_OFFSET,r16
240 add r2 = TI_FLAGS+IA64_TASK_SIZE,r16
385 add r2=IA64_TASK_BLOCKED_OFFSET,r16
386 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
[all …]
Dpal.S170 movl r16=PAL_PSR_BITS_TO_CLEAR
175 andcm r16=loc3,r16 // removes bits to clear from psr
183 mov r16=loc3 // r16= original psr
221 movl r16=PAL_PSR_BITS_TO_CLEAR
227 andcm r16=loc3,r16 // removes bits to clear from psr
240 mov r16=loc3 // r16= original psr
Dhead.S227 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
228 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
233 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
234 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
243 mov r16=IA64_TR_KERNEL
253 itr.i itr[r16]=r18
[all …]
Dmca_drv_asm.S20 alloc r16=ar.pfs,0,2,3,0 // make a new frame
34 mov loc0=r16
Dgate.S83 mov r16=IA64_KR(CURRENT) // M2 (12 cyc)
289 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16
293 sub r15=r16,r15
324 adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
327 ld8 r17=[r16]
328 ld8 r16=[r18] // get new rnat
372 mov ar.rnat=r16 // restore RNaT
/arch/ia64/lib/
Dstrnlen_user.S20 .save ar.lc, r16
21 mov r16=ar.lc // preserve ar.lc
43 mov ar.lc=r16 // restore ar.lc
Dxor.S34 mov r16 = in1
43 (p[0]) ld8.nta s1[0] = [r16], 8
71 mov r16 = in1
81 (p[0]) ld8.nta s1[0] = [r16], 8
111 mov r16 = in1
122 (p[0]) ld8.nta s1[0] = [r16], 8
154 mov r16 = in1
166 (p[0]) ld8.nta s1[0] = [r16], 8
/arch/parisc/kernel/
Dentry.S165 mfsp %sr7,%r16
811 copy %r30, %r16
813 STREG %r26, PT_GR26(%r16)
814 STREG %r25, PT_GR25(%r16)
815 STREG %r24, PT_GR24(%r16)
820 copy %r16, %r26
826 copy %r16, %r30
881 mfctl %cr30,%r16
882 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
883 ldo TASK_REGS(%r16),%r16
[all …]
/arch/ia64/ia32/
Delfcore32.h90 pr_reg[7] = regs->r16 & 0xffff; \
91 pr_reg[8] = (regs->r16 >> 16) & 0xffff; \
92 pr_reg[9] = (regs->r16 >> 32) & 0xffff; \
93 pr_reg[10] = (regs->r16 >> 48) & 0xffff; \
Dia32_entry.S36 alloc r16=ar.pfs,5,2,6,0
39 mov loc1=r16 // save ar.pfs across do_fork
122 movl r16=ia32_syscall_table
130 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
132 ld8 r16=[r16]
135 mov b6=r16
149 alloc r16=ar.pfs,2,2,4,0;;
156 alloc r16=ar.pfs,2,2,4,0
161 mov loc1=r16 // save ar.pfs across do_fork
/arch/powerpc/kvm/
Dbooke_interrupts.S136 stw r16, VCPU_GPR(r16)(r4)
214 lwz r16, VCPU_GPR(r16)(r4)
244 stw r16, VCPU_GPR(r16)(r4)
264 lwz r16, HOST_NV_GPR(r16)(r1)
305 stw r16, HOST_NV_GPR(r16)(r1)
325 lwz r16, VCPU_GPR(r16)(r4)
/arch/ia64/hp/sim/boot/
Dboot_head.S117 mov r16=0xffff /* implemented PMC */
121 st8 [r29]=r16,16 /* store implemented PMC */
129 mov r16=0xf0 /* cycles count capable PMC */
135 st8 [r29]=r16,16 /* store cycles capable */

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