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Searched refs:setbits32 (Results 1 – 15 of 15) sorted by relevance

/arch/powerpc/platforms/8xx/
Dmpc885ads_setup.c54 setbits32(&bcsr[1], BCSR1_PCCEN); in pcmcia_hw_setup()
97 setbits32(&bcsr[1], reg); in pcmcia_set_voltage()
208 setbits32(&bcsr[1], BCSR1_RS232EN_2); in mpc885ads_setup_arch()
214 setbits32(bcsr5, BCSR5_MII1_RST); in mpc885ads_setup_arch()
220 setbits32(bcsr5, BCSR5_MII2_RST); in mpc885ads_setup_arch()
224 setbits32(bcsr5, BCSR5_MII2_EN); in mpc885ads_setup_arch()
230 setbits32(&bcsr[4], BCSR4_ETH10_RST); in mpc885ads_setup_arch()
232 setbits32(&bcsr[1], BCSR1_ETHEN); in mpc885ads_setup_arch()
Dm8xx_setup.c109 setbits32(&clk_r2->car_sccr, 0x02000000); in mpc8xx_calibrate_decr()
212 setbits32(&clk_r->car_plprcr, 0x00000080); in mpc8xx_restart()
/arch/powerpc/sysdev/
Dcpm2.c335 setbits32(&iop[port].dir, pin); in cpm2_set_pin()
340 setbits32(&iop[port].par, pin); in cpm2_set_pin()
345 setbits32(&iop[port].sor, pin); in cpm2_set_pin()
350 setbits32(&iop[port].odr, pin); in cpm2_set_pin()
Dcpm1.c69 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); in cpm_unmask_irq()
191 setbits32(&cpic_reg->cpic_cicr, CICR_IEN); in cpm_pic_init()
319 setbits32(&iop->dir, pin); in cpm1_set_pin32()
324 setbits32(&iop->par, pin); in cpm1_set_pin32()
337 setbits32(&iop->sor, pin); in cpm1_set_pin32()
342 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); in cpm1_set_pin32()
711 setbits32(&iop->dir, pin_mask); in cpm1_gpio32_dir_out()
Dppc4xx_gpio.c90 setbits32(&regs->or, GPIO_MASK(gpio)); in __ppc4xx_gpio_set()
157 setbits32(&regs->tcr, GPIO_MASK(gpio)); in ppc4xx_gpio_dir_out()
Dfsl_rio.c692 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); in rio_open_inb_mbox()
695 setbits32(&priv->msg_regs->imr, 0x1); in rio_open_inb_mbox()
797 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI); in rio_hw_get_inb_message()
861 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI); in fsl_rio_dbell_handler()
1114 setbits32(priv->regs_win + RIO_CCSR, 0x02000000); in fsl_rio_setup()
1116 setbits32(priv->regs_win + RIO_CCSR, 0x00600000); in fsl_rio_setup()
Dmpc8xxx_gpio.c107 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); in mpc8xxx_gpio_dir_out()
Dcpm_common.c295 setbits32(&iop->dir, pin_mask); in cpm2_gpio32_dir_out()
/arch/powerpc/platforms/82xx/
Dmpc8272_ads.c148 setbits32(&bcsr[1], BCSR1_FETH_RST); in mpc8272_ads_setup_arch()
151 setbits32(&bcsr[3], BCSR3_FETH2_RST); in mpc8272_ads_setup_arch()
Dpq2fads.c142 setbits32(&bcsr[1], BCSR1_FETH_RST); in pq2fads_setup_arch()
145 setbits32(&bcsr[3], BCSR3_FETH2_RST); in pq2fads_setup_arch()
Dpq2.c29 setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); in pq2_restart()
Dpq2ads-pci-pic.c50 setbits32(&priv->regs->mask, 1 << irq); in pq2ads_pci_mask_irq()
/arch/powerpc/sysdev/qe_lib/
Ducc.c112 setbits32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
/arch/powerpc/platforms/83xx/
Dmpc836x_mds.c130 setbits32(immap, 0x0c003000); in mpc836x_mds_setup_arch()
/arch/powerpc/include/asm/
Dio.h743 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) macro