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Searched refs:write_c0_derraddr1 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/cavium-octeon/
Dsetup.c457 write_c0_derraddr1(0); in octeon_user_io_init()
/arch/mips/include/asm/
Dmipsregs.h973 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) macro