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Searched refs:BIT1 (Results 1 – 21 of 21) sorted by relevance

/drivers/scsi/
Dtmscsim.h190 #define BIT1 0x00000002 macro
195 #define UNIT_INFO_CHANGED BIT1
201 #define SCSI_SUPPORT BIT1
207 #define SRB_READY BIT1
224 #define ABORTION BIT1
232 #define RESET_DETECT BIT1
244 #define ABORT_DEV BIT1
279 #define SYNC_NEGO_DONE BIT1
334 #define SYNC_NEGO_ BIT1
341 #define GREATER_1G BIT1
[all …]
Ddc395x.h74 #define BIT1 0x00000002 macro
79 #define UNIT_INFO_CHANGED BIT1
85 #define SCSI_SUPPORT BIT1
121 #define RESET_DETECT BIT1
129 #define ABORTION BIT1
141 #define ABORT_DEV BIT1
174 #define SYNC_NEGO_DONE BIT1
630 #define GREATER_1G BIT1
/drivers/video/via/
Dlcd.c490 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
749 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); in load_lcd_k400_patch_tbl()
750 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); in load_lcd_k400_patch_tbl()
822 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); in load_lcd_p880_patch_tbl()
823 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); in load_lcd_p880_patch_tbl()
950 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
1011 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
1110 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
1126 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3); in integrated_lvds_disable()
1160 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
[all …]
Dhw.c734 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
744 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
747 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
754 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
755 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
787 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
794 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
801 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
856 BIT0 + BIT1 + BIT4); in set_dvi_output_path()
860 BIT0 + BIT1 + BIT4); in set_dvi_output_path()
[all …]
Dvia_utility.c183 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
Ddvi.c70 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
77 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
Dshare.h35 #define BIT1 0x02 macro
Dviafbdev.c1771 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1; in viafb_dvp0_proc_read()
1809 reg_val << 1, BIT1); in viafb_dvp0_proc_write()
/drivers/staging/wlan-ng/
Dp80211hdr.h169 #define WLAN_GET_FC_PVER(n) (((u16)(n)) & (BIT0 | BIT1))
204 #define WLAN_GET_SEQ_FRGNUM(n) (((u16)(n)) & (BIT0|BIT1|BIT2|BIT3))
205 #define WLAN_GET_SEQ_SEQNUM(n) ((((u16)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
Dhfa384x.h99 #define HFA384x_WEPFLAGS_EXCLUDE ((u16)BIT1)
255 #define HFA384x_CMD_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
258 #define HFA384x_STATUS_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
262 …FSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1))
272 #define HFA384x_EVSTAT_TX ((u16)BIT1)
287 #define HFA384x_intEN_TX ((u16)BIT1)
298 #define HFA384x_EVACK_TX ((u16)BIT1)
885 #define HFA384x_HOSTAUTHASSOC_HOSTASSOC BIT1
888 #define HFA384x_WHAHANDLING_PASSTHROUGH BIT1
1520 #define HFA384x_TESTRESULT_LFO_FAIL BIT1
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Dp80211ioctl.h90 #define P80211_NL_MCAST_GRP_SNIFF BIT1 /* Sniffer messages */
Dwlan_compat.h56 #define BIT1 0x00000002 macro
Dp80211netdev.h162 #define HOSTWEP_DEFAULTKEY_MASK (BIT1|BIT0)
Dprism2mib.c1060 if ( BIT1 & (*rate) ) { in prism2mgmt_get_oprateset()
1118 *rate |= BIT1; in prism2mgmt_set_oprateset()
Dp80211mgmt.h220 #define WLAN_GET_MGMT_CAP_INFO_IBSS(n) (((n) & BIT1) >> 1)
Dprism2mgmt.c98 (((n)&~BIT7) == 4) ? BIT1 : \
/drivers/staging/rtl8187se/
Dr8180_hw.h27 #define BIT1 0x00000002 macro
256 #define RF_SW_CFG_SI BIT1
945 #define PWR_METER_EN BIT1
/drivers/char/
Dsynclink_gt.c221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
377 #define MASK_PARITY BIT1
1866 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1867 if (status & BIT1) in rx_async()
1874 if (status & BIT1) in rx_async()
2055 if (status & BIT1) { in dcd_change()
3728 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3741 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3805 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
3830 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
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Dsynclink.c498 #define IO_PIN BIT1
517 #define RXSTATUS_OVERRUN BIT1
555 #define TXSTATUS_UNDERRUN BIT1
575 #define MISCSTATUS_BRG1_ZERO BIT1
601 #define SICR_BRG1_ZERO BIT1
635 #define TXSTATUS_UNDERRUN BIT1
640 #define DICR_RECEIVE BIT1
1605 usc_OutDmaReg( info, CDIR, BIT9+BIT1 ); in mgsl_isr_receive_dma()
5265 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5328 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
[all …]
Dsynclinkmp.c418 #define TXRDYE BIT1
428 #define BRKD BIT1
429 #define ABTD BIT1
430 #define GAPD BIT1
2606 if (status & BIT1 << shift) in synclinkmp_interrupt()
2615 if (dmastatus & BIT1 << shift) in synclinkmp_interrupt()
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4308 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { in tx_load_fifo()
4402 RegValue |= BIT1; in async_mode()
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/drivers/char/pcmcia/
Dsynclink_cs.c306 #define IRQ_OVERRUN BIT1 // receive frame overflow
313 #define CTS BIT1 // CTS state
316 #define PVR_DSR BIT1
736 #define CMD_TXEOM BIT1 // transmit end message
1241 if (gis & (BIT1 + BIT0)) { in mgslpc_isr()
1293 if (pis & BIT1) in mgslpc_isr()
3082 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); in loopback_enable()
3217 val |= BIT1; in hdlc_mode()
3236 val |= BIT2 + BIT1; in hdlc_mode()
3662 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()