Searched refs:BIT11 (Results 1 – 10 of 10) sorted by relevance
180 #define BIT11 0x00000800 macro217 #define SRB_COMPLETED BIT11
64 #define BIT11 0x00000800 macro
66 #define BIT11 0x00000800 macro
175 #define WLAN_GET_FC_RETRY(n) ((((u16)(n)) & (BIT11)) >> 11)
102 #define HFA384x_WEPFLAGS_DISALLOW_MIXED ((u16)BIT11)250 #define HFA384x_CMD_AINFO ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))257 #define HFA384x_STATUS_RESULT ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))262 #define HFA384x_OFFSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | B…1614 #define HFA384x_TX_PRST ((u16)BIT11)
408 #define IRQ_TXUNDER BIT11 /* HDLC */4139 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()4140 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4143 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4144 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4203 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()4204 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4207 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4208 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
547 #define TCSR_UNDERWAIT BIT11565 #define MISCSTATUS_RI_LATCHED BIT11587 #define SICR_RI_ACTIVE BIT11589 #define SICR_RI (BIT11+BIT10)4991 RegValue |= BIT11; in usc_set_sdlc_mode()5189 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()5190 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break; in usc_set_sdlc_mode()
37 #define BIT11 0x00000800 macro
1450 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1); in ZEBRA_Config_85BASIC_HardCode()1452 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9); in ZEBRA_Config_85BASIC_HardCode()
298 #define IRQ_TIMER BIT11 // timer interrupt