Searched refs:BIT12 (Results 1 – 9 of 9) sorted by relevance
179 #define BIT12 0x00001000 macro218 #define SRB_ABORT_SENT BIT12
63 #define BIT12 0x00001000 macro
67 #define BIT12 0x00001000 macro
176 #define WLAN_GET_FC_PWRMGT(n) ((((u16)(n)) & (BIT12)) >> 12)
250 #define HFA384x_CMD_AINFO ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))257 #define HFA384x_STATUS_RESULT ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))1613 #define HFA384x_TX_CFPOLL ((u16)BIT12)
564 #define MISCSTATUS_TXC BIT12585 #define SICR_TXC_INACTIVE BIT12586 #define SICR_TXC (BIT13+BIT12)1854 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()4712 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()4746 RegValue |= BIT12; in usc_set_sdlc_mode()4788 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()4863 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()5194 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break; in usc_set_sdlc_mode()6069 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); in usc_set_async_mode()[all …]
407 #define IRQ_TXIDLE BIT124141 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4142 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4143 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4144 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4205 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()4206 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4207 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4208 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
38 #define BIT12 0x00001000 macro
297 #define IRQ_UNDERRUN BIT12 // transmit data underrun