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Searched refs:BIT2 (Results 1 – 19 of 19) sorted by relevance

/drivers/scsi/
Dtmscsim.h189 #define BIT2 0x00000004 macro
196 #define FORMATING_MEDIA BIT2
202 #define ASPI_SUPPORT BIT2
208 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
225 #define OVER_RUN BIT2
233 #define RESET_DONE BIT2
243 #define RESET_DEV0 BIT2
280 #define WIDE_ENABLE BIT2 /* Not used ;-) */
335 #define EN_DISCONNECT_ BIT2
342 #define RST_SCSI_BUS BIT2
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Ddc395x.h73 #define BIT2 0x00000004 macro
80 #define FORMATING_MEDIA BIT2
86 #define ASPI_SUPPORT BIT2
122 #define RESET_DONE BIT2
130 #define OVER_RUN BIT2
140 #define RESET_DEV0 BIT2
175 #define WIDE_NEGO_ENABLE BIT2
631 #define RST_SCSI_BUS BIT2
/drivers/staging/wlan-ng/
Dp80211hdr.h170 #define WLAN_GET_FC_FTYPE(n) ((((u16)(n)) & (BIT2 | BIT3)) >> 2)
204 #define WLAN_GET_SEQ_FRGNUM(n) (((u16)(n)) & (BIT0|BIT1|BIT2|BIT3))
205 #define WLAN_GET_SEQ_SEQNUM(n) ((((u16)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
Dp80211ioctl.h91 #define P80211_NL_MCAST_GRP_DIST BIT2 /* Distribution system messages */
Dhfa384x.h255 #define HFA384x_CMD_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
258 #define HFA384x_STATUS_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
262 …FSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1))
271 #define HFA384x_EVSTAT_TXEXC ((u16)BIT2)
286 #define HFA384x_intEN_TXEXC ((u16)BIT2)
297 #define HFA384x_EVACK_TXEXC ((u16)BIT2)
1521 #define HFA384x_TESTRESULT_VR_HF0_FAIL BIT2
1609 #define HFA384x_TXSTATUS_DISCON ((u16)BIT2)
1619 #define HFA384x_TX_TXEX ((u16)BIT2)
Dwlan_compat.h57 #define BIT2 0x00000004 macro
Dprism2mib.c1067 if ( BIT2 & (*rate) ) { in prism2mgmt_get_oprateset()
1121 *rate |= BIT2; in prism2mgmt_set_oprateset()
Dp80211mgmt.h221 #define WLAN_GET_MGMT_CAP_INFO_CFPOLLABLE(n) (((n) & BIT2) >> 2)
Dprism2mgmt.c99 (((n)&~BIT7) == 11) ? BIT2 : \
/drivers/video/via/
Dlcd.c490 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
753 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc); in load_lcd_k400_patch_tbl()
826 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc); in load_lcd_p880_patch_tbl()
950 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
1011 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
1126 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3); in integrated_lvds_disable()
1196 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3); in integrated_lvds_enable()
Dhw.c744 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
747 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
754 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
794 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
801 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
863 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3); in set_dvi_output_path()
970 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
1055 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1583 outb(RegTemp | (BIT2 + BIT3), VIAWMisc); in viafb_set_vclock()
2743 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); in viafb_set_dpa_gfx()
Dshare.h36 #define BIT2 0x04 macro
Dviafbdev.c1774 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2; in viafb_dvp0_proc_read()
1815 reg_val << 2, BIT2); in viafb_dvp0_proc_write()
/drivers/char/
Dsynclink_gt.c220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
2020 if (status & BIT2) { in cts_change()
2224 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
3757 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3806 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
3831 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
3842 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3845 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
3861 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3923 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */ in tdma_start()
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Dsynclink.c497 #define TRANSMIT_DATA BIT2
515 #define RXSTATUS_ABORT BIT2
516 #define RXSTATUS_PARITY_ERROR BIT2
554 #define TXSTATUS_ALL_SENT BIT2
574 #define MISCSTATUS_DPLL_NO_SYNC BIT2
600 #define SICR_DPLL_NO_SYNC BIT2
634 #define TXSTATUS_ALL_SENT BIT2
1660 if ( status & BIT2 ) { in mgsl_isr_transmit_dma()
5468 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 ); in usc_process_rxoverrun_sync()
5557 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 ); in usc_start_receiver()
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Dsynclinkmp.c427 #define CDCD BIT2
443 #define CRCE BIT2
2608 if (status & BIT2 << shift) in synclinkmp_interrupt()
2617 if (dmastatus & BIT2 << shift) in synclinkmp_interrupt()
4416 case 7: RegValue |= BIT4 + BIT2; break; in async_mode()
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4553 RegValue |= BIT2 + BIT1; in hdlc_mode()
4757 if ( !(status & BIT2)) in get_signals()
4915 status &= ~BIT2; in rx_get_frame()
4929 if (status & (BIT6+BIT5+BIT3+BIT2)) { in rx_get_frame()
/drivers/char/pcmcia/
Dsynclink_cs.c305 #define IRQ_DCD BIT2 // carrier detect status change
312 #define CEC BIT2 // command executing
317 #define PVR_RI BIT2
743 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) { in wait_command_complete()
1248 if (gis & (BIT3 + BIT2)) in mgslpc_isr()
1295 if (pis & BIT2) in mgslpc_isr()
3010 val |= BIT2; in enable_auxclk()
3082 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0); in loopback_enable()
3153 val |= BIT2; in hdlc_mode()
3176 val |= BIT4 + BIT2; in hdlc_mode()
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/drivers/staging/rtl8187se/
Dr8180_hw.h28 #define BIT2 0x00000004 macro
Dr8185b_init.c2095 write_nic_byte(dev, PHYPR, (u1DA | BIT2) ); in MacConfig_85BASIC()