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Searched refs:BIT4 (Results 1 – 18 of 18) sorted by relevance

/drivers/scsi/
Dtmscsim.h187 #define BIT4 0x00000010 macro
210 #define SRB_MSGIN_MULTI BIT4
227 #define PARITY_ERROR BIT4
242 #define ENABLE_TIMER BIT4
282 #define EN_TAG_QUEUEING BIT4
337 #define TAG_QUEUEING_ BIT4
344 #define NO_SEEK BIT4
392 #define COUNT_2_ZERO BIT4
401 #define SERVICE_REQUEST BIT4
424 #define PARITY_ERR_REPO BIT4
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Ddc395x.h71 #define BIT4 0x00000010 macro
132 #define PARITY_ERROR BIT4
139 #define ENABLE_TIMER BIT4
177 #define WIDE_NEGO_STATE BIT4
633 #define NO_SEEK BIT4
/drivers/video/via/
Dhw.c715 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); in set_crt_output_path()
735 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
756 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
819 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); in set_dvi_output_path()
823 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); in set_dvi_output_path()
843 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); in set_dvi_output_path()
845 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); in set_dvi_output_path()
848 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); in set_dvi_output_path()
854 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); in set_dvi_output_path()
856 BIT0 + BIT1 + BIT4); in set_dvi_output_path()
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Dviafbdev.c525 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); in viafb_blank()
530 viafb_write_reg_mask(CR36, VIACR, 0x10, BIT4 + BIT5); in viafb_blank()
535 viafb_write_reg_mask(CR36, VIACR, 0x20, BIT4 + BIT5); in viafb_blank()
540 viafb_write_reg_mask(CR36, VIACR, 0x30, BIT4 + BIT5); in viafb_blank()
1773 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 | in viafb_dvp0_proc_read()
1813 reg_val << 3, BIT4); in viafb_dvp0_proc_write()
Ddvi.c86 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
Dshare.h38 #define BIT4 0x10 macro
Dlcd.c1371 bdual = BIT4; in fill_lcd_format()
1375 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0); in fill_lcd_format()
/drivers/staging/wlan-ng/
Dwlan_compat.h59 #define BIT4 0x00000010 macro
Dhfa384x.h100 #define HFA384x_WEPFLAGS_DISABLE_TXCRYPT ((u16)BIT4)
255 #define HFA384x_CMD_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
258 #define HFA384x_STATUS_CMDCODE ((u16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0))
262 #define HFA384x_OFFSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | B…
269 #define HFA384x_EVSTAT_CMD ((u16)BIT4)
284 #define HFA384x_intEN_CMD ((u16)BIT4)
295 #define HFA384x_EVACK_CMD ((u16)BIT4)
1618 #define HFA384x_TX_STRUCTYPE ((u16)(BIT4 | BIT3))
Dp80211netdev.h163 #define HOSTWEP_DECRYPT BIT4
Dp80211hdr.h171 #define WLAN_GET_FC_FSTYPE(n) ((((u16)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
Dp80211mgmt.h223 #define WLAN_GET_MGMT_CAP_INFO_PRIVACY(n) (((n) & BIT4) >> 4)
/drivers/char/
Dsynclink.c495 #define RECEIVE_DATA BIT4
512 #define RXSTATUS_RXBOUND BIT4
551 #define TXSTATUS_EOF_SENT BIT4
552 #define TXSTATUS_EOM_SENT BIT4
572 #define MISCSTATUS_CTS BIT4
597 #define SICR_CTS_INACTIVE BIT4
598 #define SICR_CTS (BIT5+BIT4)
632 #define TXSTATUS_EOF BIT4
4752 RegValue |= BIT4; in usc_set_sdlc_mode()
5024 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
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Dsynclinkmp.c424 #define SYNCD BIT4
425 #define FLGD BIT4
440 #define FRME BIT4
441 #define RBIT BIT4
2623 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2627 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4416 case 7: RegValue |= BIT4 + BIT2; break; in async_mode()
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4549 RegValue |= BIT4; in hdlc_mode()
4551 RegValue |= BIT4; in hdlc_mode()
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Dsynclink_gt.c380 #define MASK_OVERRUN BIT4
416 #define IRQ_RI BIT4
2183 if (status & (BIT5 + BIT4)) { in isr_rdma()
2208 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4011 case 6: val |= BIT4; break; in async_mode()
4013 case 8: val |= BIT5 + BIT4; break; in async_mode()
4051 case 6: val |= BIT4; break; in async_mode()
4053 case 8: val |= BIT5 + BIT4; break; in async_mode()
4159 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4160 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
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/drivers/char/pcmcia/
Dsynclink_cs.c734 #define CMD_START_TIMER BIT4
3086 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); in loopback_enable()
3173 val |= BIT4; in hdlc_mode()
3176 val |= BIT4 + BIT2; in hdlc_mode()
3179 val |= BIT4 + BIT3; in hdlc_mode()
3215 val |= BIT4; in hdlc_mode()
3582 val |= BIT4; in async_mode()
3739 if (!(status & BIT7) || (status & BIT4)) in rx_get_frame()
/drivers/staging/rtl8187se/
Dr8180_hw.h30 #define BIT4 0x00000010 macro
Dr8180_core.c6747 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;