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Searched refs:BIT7 (Results 1 – 20 of 20) sorted by relevance

/drivers/scsi/
Dtmscsim.h184 #define BIT7 0x00000080 macro
213 #define SRB_DISCONNECT BIT7
239 #define DATAOUT BIT7
363 #define DMA_COMMAND BIT7
389 #define INTERRUPT BIT7
398 #define SCSI_RESET BIT7
422 #define EXTENDED_TIMING BIT7
432 #define ID_MSG_CHECK BIT7
440 #define EATER_25NS BIT7
442 #define EATER_0NS (BIT7+BIT6)
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Ddc395x.h68 #define BIT7 0x00000080 macro
136 #define DATAOUT BIT7
/drivers/video/via/
Dhw.c537 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); in viafb_lock_crt()
542 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); in viafb_unlock_crt()
723 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); in set_crt_output_path()
821 BIT5 + BIT7); in set_dvi_output_path()
825 BIT5 + BIT7); in set_dvi_output_path()
828 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6); in set_dvi_output_path()
837 BIT0 + BIT5 + BIT7); in set_dvi_output_path()
840 BIT0 + BIT5 + BIT7); in set_dvi_output_path()
970 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
1045 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); in load_fix_bit_crtc_reg()
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Dvia_utility.c151 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_set_gamma_table()
161 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_set_gamma_table()
206 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_get_gamma_table()
216 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_get_gamma_table()
Dlcd.c521 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
533 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); in load_lcd_scaling()
741 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); in load_lcd_k400_patch_tbl()
746 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); in load_lcd_k400_patch_tbl()
814 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); in load_lcd_p880_patch_tbl()
819 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); in load_lcd_p880_patch_tbl()
1113 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
1122 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
1132 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); in integrated_lvds_disable()
1144 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
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Ddvi.c80 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
87 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
676 viafb_write_reg_mask(CR91, VIACR, 0, BIT7); in viafb_dvi_enable()
Dviafbdev.c328 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7); in viafb_setcolreg()
332 viafb_write_reg_mask(SR15, VIASR, 0, BIT7); in viafb_setcolreg()
431 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7); in viafb_setcmap()
435 viafb_write_reg_mask(SR15, VIASR, 0, BIT7); in viafb_setcmap()
Dshare.h41 #define BIT7 0x80 macro
/drivers/staging/wlan-ng/
Dp80211hdr.h171 #define WLAN_GET_FC_FSTYPE(n) ((((u16)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
214 #define DOT11_RATE5_ISBASIC_GET(r) (((u8)(r)) & BIT7)
Dprism2mgmt.c97 #define p80211rate_to_p2bit(n) ((((n)&~BIT7) == 2) ? BIT0 : \
98 (((n)&~BIT7) == 4) ? BIT1 : \
99 (((n)&~BIT7) == 11) ? BIT2 : \
100 (((n)&~BIT7) == 22) ? BIT3 : 0)
Dwlan_compat.h62 #define BIT7 0x00000080 macro
Dp80211netdev.h166 #define HOSTWEP_EXCLUDEUNENCRYPTED BIT7
Dhfa384x.h101 #define HFA384x_WEPFLAGS_DISABLE_RXCRYPT ((u16)BIT7)
262 #define HFA384x_OFFSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | B…
267 #define HFA384x_EVSTAT_INFO ((u16)BIT7)
282 #define HFA384x_intEN_INFO ((u16)BIT7)
293 #define HFA384x_EVACK_INFO ((u16)BIT7)
1522 #define HFA384x_HOST_FIRM_COORDINATE BIT7
1616 #define HFA384x_TX_NOENCRYPT ((u16)BIT7)
Dp80211mgmt.h227 #define WLAN_GET_MGMT_CAP_INFO_AGILITY(n) (((n) & BIT7) >> 7)
/drivers/char/pcmcia/
Dsynclink_cs.c302 #define IRQ_RXEOM BIT7 // receive message end
731 #define CMD_RXFIFO BIT7 // release current rx FIFO
981 if (status & (BIT7 + BIT6)) { in rx_ready_async()
982 if (status & BIT7) in rx_ready_async()
993 if (status & BIT7) in rx_ready_async()
1291 if (gis & BIT7) { in mgslpc_isr()
1539 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1541 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
3248 val |= BIT7 + BIT6; in hdlc_mode()
3660 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
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/drivers/char/
Dsynclink.c508 #define RXSTATUS_EXITED_HUNT BIT7
548 #define TXSTATUS_PREAMBLE_SENT BIT7
569 #define MISCSTATUS_DCD_LATCHED BIT7
593 #define SICR_DCD_ACTIVE BIT7
595 #define SICR_DCD (BIT7+BIT6)
629 #define TXSTATUS_PREAMBLE_SENT BIT7
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); in mgsl_break()
2915 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); in mgsl_break()
5236 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6)); in usc_enable_loopback()
5275 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6)); in usc_enable_loopback()
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Dsynclink_gt.c413 #define IRQ_DSR BIT7
2803 val |= BIT7; in set_interface()
2805 val &= ~BIT7; in set_interface()
4001 val |= BIT7; in async_mode()
4134 val |= BIT7; in sync_mode()
4242 val |= BIT7; /* 100, txclk = DPLL Input */ in sync_mode()
4265 val = BIT7; break; in sync_mode()
4268 val = BIT7 + BIT6; break; in sync_mode()
4392 val |= BIT7 + BIT6 + BIT5; /* 1110 */ in msc_set_vcr()
Dsynclinkmp.c416 #define TXINTE BIT7
422 #define UDRN BIT7
435 #define EOM BIT7
2625 if (timerstatus0 & (BIT7 | BIT6)) in synclinkmp_interrupt()
2629 if (timerstatus1 & (BIT7 | BIT6)) in synclinkmp_interrupt()
4581 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ in hdlc_mode()
4582 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ in hdlc_mode()
4583 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ in hdlc_mode()
/drivers/staging/rtl8187se/
Dr8180_hw.h33 #define BIT7 0x00000080 macro
Dr8185b_init.c338 if((u1bTmp & BIT7) == 0) in PlatformIOWrite4Byte()