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Searched refs:BIT8 (Results 1 – 13 of 13) sorted by relevance

/drivers/staging/wlan-ng/
Dhfa384x.h107 #define HFA384x_WEPFLAGS_FIRMWARE_WPA ((u16)BIT8)
250 #define HFA384x_CMD_AINFO ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))
251 #define HFA384x_CMD_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
252 #define HFA384x_CMD_RECL ((u16)BIT8)
253 #define HFA384x_CMD_WRITE ((u16)BIT8)
254 #define HFA384x_CMD_PROGMODE ((u16)(BIT9 | BIT8))
257 #define HFA384x_STATUS_RESULT ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))
262 #define HFA384x_OFFSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | B…
1615 #define HFA384x_TX_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
1697 #define HFA384x_RXSTATUS_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
Dwlan_compat.h63 #define BIT8 0x00000100 macro
Dp80211hdr.h172 #define WLAN_GET_FC_TODS(n) ((((u16)(n)) & (BIT8)) >> 8)
/drivers/scsi/
Dtmscsim.h183 #define BIT8 0x00000100 macro
214 #define SRB_DATA_XFER BIT8
Ddc395x.h67 #define BIT8 0x00000100 macro
/drivers/char/
Dsynclink.c506 #define RXSTATUS_SHORT_FRAME BIT8
507 #define RXSTATUS_CODE_VIOLATION BIT8
568 #define MISCSTATUS_DSR BIT8
591 #define SICR_DSR_INACTIVE BIT8
592 #define SICR_DSR (BIT9+BIT8)
1649 usc_OutDmaReg(info, CDIR, BIT8+BIT0 ); in mgsl_isr_transmit_dma()
4861 RegValue |= BIT9 + BIT8; in usc_set_sdlc_mode()
4863 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5030 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
5034 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break; in usc_set_sdlc_mode()
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Dsynclink_gt.c412 #define IRQ_RXOVER BIT8
2301 if (gsr & (BIT8 << i)) in slgt_interrupt()
4006 val |= BIT8; in async_mode()
4046 val |= BIT8; in async_mode()
4150 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4214 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4827 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
/drivers/staging/rtl8187se/
Dr8180_hw.h34 #define BIT8 0x00000100 macro
/drivers/staging/rt2860/
Drtmp.h97 extern UCHAR BIT8[8];
1693 pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] &= ~BIT8[0];
1697 pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] |= BIT8[0];
1703 ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] &= (~BIT8[bit_offset]); }
1709 ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] |= BIT8[bit_offset]; }
/drivers/staging/rt2870/
Drtmp.h198 extern UCHAR BIT8[8];
1638 pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] &= ~BIT8[0];
1642 pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] |= BIT8[0];
1648 ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] &= (~BIT8[bit_offset]); }
1654 ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] |= BIT8[bit_offset]; }
/drivers/staging/rt2860/common/
Drtmp_init.c44 UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; variable
/drivers/staging/rt2870/common/
Drtmp_init.c45 UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; variable
/drivers/char/pcmcia/
Dsynclink_cs.c301 #define IRQ_TXFIFO BIT8 // transmit pool ready