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Searched refs:BIT9 (Results 1 – 10 of 10) sorted by relevance

/drivers/scsi/
Dtmscsim.h182 #define BIT9 0x00000200 macro
215 #define SRB_XFERPAD BIT9
Ddc395x.h66 #define BIT9 0x00000200 macro
/drivers/staging/wlan-ng/
Dwlan_compat.h64 #define BIT9 0x00000200 macro
Dhfa384x.h108 #define HFA384x_WEPFLAGS_HOST_MIC ((u16)BIT9)
250 #define HFA384x_CMD_AINFO ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))
251 #define HFA384x_CMD_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
254 #define HFA384x_CMD_PROGMODE ((u16)(BIT9 | BIT8))
257 #define HFA384x_STATUS_RESULT ((u16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8))
262 #define HFA384x_OFFSET_DATAOFF ((u16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | B…
1615 #define HFA384x_TX_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
1697 #define HFA384x_RXSTATUS_MACPORT ((u16)(BIT10 | BIT9 | BIT8))
Dp80211hdr.h173 #define WLAN_GET_FC_FROMDS(n) ((((u16)(n)) & (BIT9)) >> 9)
/drivers/char/
Dsynclink.c567 #define MISCSTATUS_DSR_LATCHED BIT9
590 #define SICR_DSR_ACTIVE BIT9
592 #define SICR_DSR (BIT9+BIT8)
1605 usc_OutDmaReg( info, CDIR, BIT9+BIT1 ); in mgsl_isr_receive_dma()
1714 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()
4786 RegValue |= BIT9; in usc_set_sdlc_mode()
4788 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4861 RegValue |= BIT9 + BIT8; in usc_set_sdlc_mode()
4863 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5032 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
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Dsynclink_gt.c410 #define IRQ_RXIDLE BIT9 /* HDLC */
411 #define IRQ_RXBREAK BIT9 /* async */
4004 val |= BIT9; in async_mode()
4044 val |= BIT9; in async_mode()
4149 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4150 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4213 case HDLC_CRC_16_CCITT: val |= BIT9; break; in sync_mode()
4214 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()
4827 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
/drivers/staging/rtl8187se/
Dr8180_hw.h35 #define BIT9 0x00000200 macro
Dr8185b_init.c1450 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1); in ZEBRA_Config_85BASIC_HardCode()
1452 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9); in ZEBRA_Config_85BASIC_HardCode()
/drivers/char/pcmcia/
Dsynclink_cs.c300 #define IRQ_TXREPEAT BIT9 // tx message repeat