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Searched refs:BIT_2 (Results 1 – 9 of 9) sorted by relevance

/drivers/scsi/
Dqla1280.h28 #define BIT_2 0x4 macro
130 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
139 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
144 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
149 #define RISC_INT BIT_2 /* RISC interrupt */
156 #define NV_DATA_OUT BIT_2
166 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
183 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
331 #define NV_START_BIT BIT_2
575 #define RF_BAD_HEADER BIT_2 /* Bad header. */
Dqla1280.c1154 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1665 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1727 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()
1744 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()
1866 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1880 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2174 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2215 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()
2222 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2236 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb); in qla1280_nvram_config()
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/drivers/scsi/qla2xxx/
Dqla_fw.h403 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
446 #define TMF_DSD_LIST_ENABLE BIT_2
730 #define TCF_CLEAR_TASK_SET BIT_2
845 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
909 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
913 #define GPDX_LED_YELLOW_ON BIT_2
1098 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1284 #define FSTATE_IS_DIAG_FW BIT_2
1300 #define VCO_DONT_RESET_UPDATE BIT_2
Dqla_def.h56 #define BIT_2 0x4 macro
206 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
245 #define NVR_DATA_OUT BIT_2
434 #define IOCTL_CMD BIT_2
666 #define MBX_2 BIT_2
757 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
888 #define NV_START_BIT BIT_2
1179 #define CF_ORDERED_TAG BIT_2
1293 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1311 #define SS_CONDITION_MET BIT_2
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Dqla_init.c998 (ha->fw_attributes & BIT_2)) { in qla2x00_setup_chip()
1087 if (ha->fw_seriallink_options[3] & BIT_2) { in qla2x00_update_fw_options()
1091 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1095 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1113 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1696 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
1703 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
1730 nv->host_p[1] = BIT_2; in qla2x00_nvram_config()
1765 nv->firmware_options[0] |= BIT_2; in qla2x00_nvram_config()
1780 nv->firmware_options[0] |= BIT_2; in qla2x00_nvram_config()
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Dqla_os.c326 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); in qla24xx_pci_info_str()
350 if (pci_bus & BIT_2) in qla24xx_pci_info_str()
355 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); in qla24xx_pci_info_str()
Dqla_mbx.c2653 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); in qla2x00_set_idma_speed()
/drivers/scsi/qla4xxx/
Dql4_def.h57 #define BIT_2 0x4 macro
Dql4_init.c738 if (ha->firmware_state & (BIT_2 | BIT_0)) in qla4xxx_flush_AENS()