Searched refs:BIT_3 (Results 1 – 10 of 10) sorted by relevance
57 #define BIT_3 0x8 macro207 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */227 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */233 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */236 #define ISR_RISC_INT BIT_3 /* RISC interrupt */244 #define NVR_DATA_IN BIT_3518 #define FO1_CTIO_RETRY BIT_3665 #define MBX_3 BIT_3867 #define GLSO_USE_DID BIT_31178 #define CF_SIMPLE_TAG BIT_3[all …]
729 #define TCF_ABORT_TASK_SET BIT_3850 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */853 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */909 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)914 #define GPDX_LED_GREEN_ON BIT_31033 #define MDBS_NON_PARTIC BIT_31285 #define FSTATE_LOGGED_IN BIT_31301 #define VCO_DIAG_FW BIT_3
1093 (BIT_4 | BIT_3)) >> 3; in qla2x00_update_fw_options()1095 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()1113 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()1709 nv->firmware_options[0] = BIT_3 | BIT_1; in qla2x00_nvram_config()1766 nv->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()1838 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); in qla2x00_nvram_config()1914 icb->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()1916 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_nvram_config()1926 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_nvram_config()1931 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_nvram_config()[all …]
505 req->options |= BIT_3; in qla25xx_update_req_que()511 req->options &= ~BIT_3; in qla25xx_update_req_que()
1865 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; in qla2x00_full_login_lip()2772 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()
1598 if (RD_REG_DWORD(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()
326 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); in qla24xx_pci_info_str()
29 #define BIT_3 0x8 macro131 #define ISP_CFG0_1040A BIT_3 /* ISP1040A */157 #define NV_DATA_IN BIT_3165 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */182 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */576 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
1154 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()1727 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()1744 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 | in qla1280_load_firmware_dma()1866 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()1880 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()2174 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()2857 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_64bit_start_scsi()3126 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_32bit_start_scsi()3749 if (pkt->entry_status & BIT_3) in qla1280_error_entry()3769 if (pkt->entry_status & (BIT_3 + BIT_2)) { in qla1280_error_entry()[all …]
58 #define BIT_3 0x8 macro161 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */