Searched refs:CSR0_CLRALL (Results 1 – 2 of 2) sorted by relevance
36 #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */ macro
273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ in ni65_set_performance()569 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); in ni65_init_lance()857 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT); in ni65_lance_reinit()885 writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */ in ni65_interrupt()887 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ in ni65_interrupt()