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Searched refs:MII_QS6612_IMR (Results 1 – 2 of 2) sorted by relevance

/drivers/net/phy/
Dqsemi.c47 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ macro
106 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
109 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
/drivers/net/
Dfec.c986 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ macro
1019 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1034 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },