Searched refs:NCR5380_read (Results 1 – 20 of 20) sorted by relevance
336 r = NCR5380_read(reg); in NCR5380_poll_politely()345 r = NCR5380_read(reg); in NCR5380_poll_politely()424 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()425 status = NCR5380_read(STATUS_REG); in NCR5380_print()426 mr = NCR5380_read(MODE_REG); in NCR5380_print()427 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()428 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()466 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()905 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) { in NCR5380_init()1177 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()[all …]
571 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()572 status = NCR5380_read(STATUS_REG); in NCR5380_print()573 mr = NCR5380_read(MODE_REG); in NCR5380_print()574 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()575 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()617 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()1205 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()1206 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()1216 if((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | in NCR5380_dma_complete()1219 printk("scsi%d: BASR %02x\n", HOSTNO, NCR5380_read(BUS_AND_STATUS_REG)); in NCR5380_dma_complete()[all …]
571 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()572 status = NCR5380_read(STATUS_REG); in NCR5380_print()573 mr = NCR5380_read(MODE_REG); in NCR5380_print()574 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()575 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()618 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()1220 if ((NCR5380_read(BUS_AND_STATUS_REG) & in NCR5380_dma_complete()1223 saved_data = NCR5380_read(INPUT_DATA_REG); in NCR5380_dma_complete()1231 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()1232 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()[all …]
584 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { in NCR5380_pread()587 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()591 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); in NCR5380_pread()597 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()608 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()617 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()627 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()635 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()638 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) in NCR5380_pread()642 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()[all …]
358 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in mac_scsi_reset_boot()366 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in mac_scsi_reset_boot()466 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()467 && !(NCR5380_read(STATUS_REG) & SR_REQ)) in macscsi_pread()469 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()470 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { in macscsi_pread()558 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pwrite()559 && (!(NCR5380_read(STATUS_REG) & SR_REQ) in macscsi_pwrite()560 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) in macscsi_pwrite()562 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) { in macscsi_pwrite()
370 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()380 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()391 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pread()395 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()420 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pwrite()431 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()439 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pwrite()443 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()
344 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()354 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()574 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & in sun3scsi_dma_finish()577 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); in sun3scsi_dma_finish()
125 #define NCR5380_read(reg) readb(T128_address(reg)) macro128 #define NCR5380_read(reg) \ macro
73 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro76 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
146 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro149 #define NCR5380_read(reg) \ macro
81 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro106 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
254 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in init_board()331 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ in pas16_hw_detect()334 if( NCR5380_read( MODE_REG ) != 0x00 ) in pas16_hw_detect()
65 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
313 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()323 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
38 #define NCR5380_read(reg) inb(port + reg) macro
49 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
852 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG))); in atari_scsi_reset_boot()860 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in atari_scsi_reset_boot()
97 #define NCR5380_read(reg) sun3scsi_read(reg) macro
30 #define NCR5380_read(reg) readb(_base + ((reg) << 2)) macro
30 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro