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Searched refs:PLX_INTCSR (Results 1 – 14 of 14) sorted by relevance

/drivers/staging/meilhaus/
Dmefirmware.c74 outl(PLX_INTCSR_LOCAL_INT2_POL, register_base_control + PLX_INTCSR); in me_xilinx_download()
89 (inl(register_base_control + PLX_INTCSR) & in me_xilinx_download()
133 outl(ME_PLX_PCI_ACTIVATE, register_base_control + PLX_INTCSR); in me_xilinx_download()
Dmeplx_reg.h32 #define PLX_INTCSR 0x4C /**< Interrupt control and status register. */ macro
Dme8200_device.c100 me8200_device->base.info.pci.reg_bases[1] + PLX_INTCSR); in me8200_pci_constructor()
Dme0600_ext_irq.c456 subdevice->intcsr = plx_reg_base + PLX_INTCSR; in me0600_ext_irq_constructor()
Dme8100_di.c667 subdevice->irq_status_reg = plx_reg_base + PLX_INTCSR; in me8100_di_constructor()
/drivers/net/wireless/orinoco/
Dorinoco_plx.c104 #define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */ macro
167 csr_reg = ioread32(card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()
170 iowrite32(csr_reg, card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()
171 csr_reg = ioread32(card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()
/drivers/staging/comedi/drivers/
Dme_daq.c64 #define PLX_INTCSR 0x4C /* PLX interrupt status register */ macro
553 writel(0x00, dev_private->plx_regbase + PLX_INTCSR); in me2600_xilinx_download()
593 value = readl(dev_private->plx_regbase + PLX_INTCSR); in me2600_xilinx_download()
596 writel(0x00, dev_private->plx_regbase + PLX_INTCSR); in me2600_xilinx_download()
606 writel(0x43, dev_private->plx_regbase + PLX_INTCSR); in me2600_xilinx_download()
Dme4000.h162 #define PLX_INTCSR 0x4C // Interrupt control and status register macro
Dme4000.c773 outl(0x10, info->plx_regbase + PLX_INTCSR); in xilinx_download()
785 if (!inl(info->plx_regbase + PLX_INTCSR) & 0x20) { in xilinx_download()
883 me4000_outl(dev, 0x43, info->plx_regbase + PLX_INTCSR); in reset_board()
/drivers/net/wireless/hostap/
Dhostap_plx.c55 #define PLX_INTCSR 0x4c /* Interrupt Control/Status Register */ macro
515 reg = inl(plx_ioaddr + PLX_INTCSR); in prism2_plx_probe()
519 plx_ioaddr + PLX_INTCSR); in prism2_plx_probe()
520 if (!(inl(plx_ioaddr + PLX_INTCSR) & in prism2_plx_probe()
/drivers/staging/me4000/
Dme4000.h165 #define PLX_INTCSR 0x4C // Interrupt control and status register macro
Dme4000.c1163 outl(0x10, info->plx_regbase + PLX_INTCSR); in me4000_xilinx_download()
1175 if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) { in me4000_xilinx_download()
1259 me4000_outl(0x43, info->plx_regbase + PLX_INTCSR); in me4000_reset_board()
/drivers/isdn/hardware/mISDN/
Dhfc_multi.h254 #define PLX_INTCSR 0x4c macro
Dhfcmulti.c2612 plx_acc = hc->plx_membase + PLX_INTCSR; in hfcmulti_interrupt()
4135 plx_acc = hc->plx_membase + PLX_INTCSR; in init_card()
4184 plx_acc = hc->plx_membase + PLX_INTCSR; in init_card()