1 /* bnx2x_reg.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2009 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * The registers description starts with the register Access type followed 10 * by size in bits. For example [RW 32]. The access types are: 11 * R - Read only 12 * RC - Clear on read 13 * RW - Read/Write 14 * ST - Statistics register (clear on read) 15 * W - Write only 16 * WB - Wide bus register - the size is over 32 bits and it should be 17 * read/write in consecutive 32 bits accesses 18 * WR - Write Clear (write 1 to clear the bit) 19 * 20 */ 21 22 23 /* [R 19] Interrupt register #0 read */ 24 #define BRB1_REG_BRB1_INT_STS 0x6011c 25 /* [RW 4] Parity mask register #0 read/write */ 26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138 27 /* [R 4] Parity register #0 read */ 28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c 29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */ 32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 33 /* [RW 23] LL RAM data. */ 34 #define BRB1_REG_LL_RAM 0x61000 35 /* [R 24] The number of full blocks. */ 36 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 37 /* [ST 32] The number of cycles that the write_full signal towards MAC #0 38 was asserted. */ 39 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 40 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 41 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 42 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was 43 asserted. */ 44 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 45 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 46 /* [RW 10] Write client 0: De-assert pause threshold. */ 47 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 48 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 49 /* [RW 10] Write client 0: Assert pause threshold. */ 50 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 51 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c 52 /* [R 24] The number of full blocks occupied by port. */ 53 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 54 /* [RW 1] Reset the design by software. */ 55 #define BRB1_REG_SOFT_RESET 0x600dc 56 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 57 #define CCM_REG_CAM_OCCUP 0xd0188 58 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 59 acknowledge output is deasserted; all other signals are treated as usual; 60 if 1 - normal activity. */ 61 #define CCM_REG_CCM_CFC_IFEN 0xd003c 62 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 63 disregarded; valid is deasserted; all other signals are treated as usual; 64 if 1 - normal activity. */ 65 #define CCM_REG_CCM_CQM_IFEN 0xd000c 66 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. 67 Otherwise 0 is inserted. */ 68 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0 69 /* [RW 11] Interrupt mask register #0 read/write */ 70 #define CCM_REG_CCM_INT_MASK 0xd01e4 71 /* [R 11] Interrupt register #0 read */ 72 #define CCM_REG_CCM_INT_STS 0xd01d8 73 /* [R 27] Parity register #0 read */ 74 #define CCM_REG_CCM_PRTY_STS 0xd01e8 75 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 77 Is used to determine the number of the AG context REG-pairs written back; 78 when the input message Reg1WbFlg isn't set. */ 79 #define CCM_REG_CCM_REG0_SZ 0xd00c4 80 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 81 disregarded; valid is deasserted; all other signals are treated as usual; 82 if 1 - normal activity. */ 83 #define CCM_REG_CCM_STORM0_IFEN 0xd0004 84 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 85 disregarded; valid is deasserted; all other signals are treated as usual; 86 if 1 - normal activity. */ 87 #define CCM_REG_CCM_STORM1_IFEN 0xd0008 88 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 89 disregarded; valid output is deasserted; all other signals are treated as 90 usual; if 1 - normal activity. */ 91 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030 92 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 93 are disregarded; all other signals are treated as usual; if 1 - normal 94 activity. */ 95 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c 96 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 97 disregarded; valid output is deasserted; all other signals are treated as 98 usual; if 1 - normal activity. */ 99 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038 100 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 101 input is disregarded; all other signals are treated as usual; if 1 - 102 normal activity. */ 103 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034 104 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 105 the initial credit value; read returns the current value of the credit 106 counter. Must be initialized to 1 at start-up. */ 107 #define CCM_REG_CFC_INIT_CRD 0xd0204 108 /* [RW 2] Auxillary counter flag Q number 1. */ 109 #define CCM_REG_CNT_AUX1_Q 0xd00c8 110 /* [RW 2] Auxillary counter flag Q number 2. */ 111 #define CCM_REG_CNT_AUX2_Q 0xd00cc 112 /* [RW 28] The CM header value for QM request (primary). */ 113 #define CCM_REG_CQM_CCM_HDR_P 0xd008c 114 /* [RW 28] The CM header value for QM request (secondary). */ 115 #define CCM_REG_CQM_CCM_HDR_S 0xd0090 116 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 117 acknowledge output is deasserted; all other signals are treated as usual; 118 if 1 - normal activity. */ 119 #define CCM_REG_CQM_CCM_IFEN 0xd0014 120 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 121 the initial credit value; read returns the current value of the credit 122 counter. Must be initialized to 32 at start-up. */ 123 #define CCM_REG_CQM_INIT_CRD 0xd020c 124 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 125 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 126 prioritised); 2 stands for weight 2; tc. */ 127 #define CCM_REG_CQM_P_WEIGHT 0xd00b8 128 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 129 acknowledge output is deasserted; all other signals are treated as usual; 130 if 1 - normal activity. */ 131 #define CCM_REG_CSDM_IFEN 0xd0018 132 /* [RC 1] Set when the message length mismatch (relative to last indication) 133 at the SDM interface is detected. */ 134 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 135 /* [RW 28] The CM header for QM formatting in case of an error in the QM 136 inputs. */ 137 #define CCM_REG_ERR_CCM_HDR 0xd0094 138 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 139 #define CCM_REG_ERR_EVNT_ID 0xd0098 140 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 141 writes the initial credit value; read returns the current value of the 142 credit counter. Must be initialized to 64 at start-up. */ 143 #define CCM_REG_FIC0_INIT_CRD 0xd0210 144 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 145 writes the initial credit value; read returns the current value of the 146 credit counter. Must be initialized to 64 at start-up. */ 147 #define CCM_REG_FIC1_INIT_CRD 0xd0214 148 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 149 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 150 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 151 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 152 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 153 #define CCM_REG_GR_ARB_TYPE 0xd015c 154 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 155 highest priority is 3. It is supposed; that the Store channel priority is 156 the compliment to 4 of the rest priorities - Aggregation channel; Load 157 (FIC0) channel and Load (FIC1). */ 158 #define CCM_REG_GR_LD0_PR 0xd0164 159 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 160 highest priority is 3. It is supposed; that the Store channel priority is 161 the compliment to 4 of the rest priorities - Aggregation channel; Load 162 (FIC0) channel and Load (FIC1). */ 163 #define CCM_REG_GR_LD1_PR 0xd0168 164 /* [RW 2] General flags index. */ 165 #define CCM_REG_INV_DONE_Q 0xd0108 166 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 167 context and sent to STORM; for a specific connection type. The double 168 REG-pairs are used in order to align to STORM context row size of 128 169 bits. The offset of these data in the STORM context is always 0. Index 170 _(0..15) stands for the connection type (one of 16). */ 171 #define CCM_REG_N_SM_CTX_LD_0 0xd004c 172 #define CCM_REG_N_SM_CTX_LD_1 0xd0050 173 #define CCM_REG_N_SM_CTX_LD_10 0xd0074 174 #define CCM_REG_N_SM_CTX_LD_11 0xd0078 175 #define CCM_REG_N_SM_CTX_LD_12 0xd007c 176 #define CCM_REG_N_SM_CTX_LD_13 0xd0080 177 #define CCM_REG_N_SM_CTX_LD_14 0xd0084 178 #define CCM_REG_N_SM_CTX_LD_15 0xd0088 179 #define CCM_REG_N_SM_CTX_LD_2 0xd0054 180 #define CCM_REG_N_SM_CTX_LD_3 0xd0058 181 #define CCM_REG_N_SM_CTX_LD_4 0xd005c 182 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 183 acknowledge output is deasserted; all other signals are treated as usual; 184 if 1 - normal activity. */ 185 #define CCM_REG_PBF_IFEN 0xd0028 186 /* [RC 1] Set when the message length mismatch (relative to last indication) 187 at the pbf interface is detected. */ 188 #define CCM_REG_PBF_LENGTH_MIS 0xd0180 189 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 190 weight 8 (the most prioritised); 1 stands for weight 1(least 191 prioritised); 2 stands for weight 2; tc. */ 192 #define CCM_REG_PBF_WEIGHT 0xd00ac 193 #define CCM_REG_PHYS_QNUM1_0 0xd0134 194 #define CCM_REG_PHYS_QNUM1_1 0xd0138 195 #define CCM_REG_PHYS_QNUM2_0 0xd013c 196 #define CCM_REG_PHYS_QNUM2_1 0xd0140 197 #define CCM_REG_PHYS_QNUM3_0 0xd0144 198 #define CCM_REG_PHYS_QNUM3_1 0xd0148 199 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 200 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 201 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 202 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 203 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 204 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 205 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 206 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 207 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 208 disregarded; acknowledge output is deasserted; all other signals are 209 treated as usual; if 1 - normal activity. */ 210 #define CCM_REG_STORM_CCM_IFEN 0xd0010 211 /* [RC 1] Set when the message length mismatch (relative to last indication) 212 at the STORM interface is detected. */ 213 #define CCM_REG_STORM_LENGTH_MIS 0xd016c 214 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 215 disregarded; acknowledge output is deasserted; all other signals are 216 treated as usual; if 1 - normal activity. */ 217 #define CCM_REG_TSEM_IFEN 0xd001c 218 /* [RC 1] Set when the message length mismatch (relative to last indication) 219 at the tsem interface is detected. */ 220 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 221 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 222 weight 8 (the most prioritised); 1 stands for weight 1(least 223 prioritised); 2 stands for weight 2; tc. */ 224 #define CCM_REG_TSEM_WEIGHT 0xd00a0 225 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 226 disregarded; acknowledge output is deasserted; all other signals are 227 treated as usual; if 1 - normal activity. */ 228 #define CCM_REG_USEM_IFEN 0xd0024 229 /* [RC 1] Set when message length mismatch (relative to last indication) at 230 the usem interface is detected. */ 231 #define CCM_REG_USEM_LENGTH_MIS 0xd017c 232 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 233 weight 8 (the most prioritised); 1 stands for weight 1(least 234 prioritised); 2 stands for weight 2; tc. */ 235 #define CCM_REG_USEM_WEIGHT 0xd00a8 236 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 237 disregarded; acknowledge output is deasserted; all other signals are 238 treated as usual; if 1 - normal activity. */ 239 #define CCM_REG_XSEM_IFEN 0xd0020 240 /* [RC 1] Set when the message length mismatch (relative to last indication) 241 at the xsem interface is detected. */ 242 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 243 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 244 weight 8 (the most prioritised); 1 stands for weight 1(least 245 prioritised); 2 stands for weight 2; tc. */ 246 #define CCM_REG_XSEM_WEIGHT 0xd00a4 247 /* [RW 19] Indirect access to the descriptor table of the XX protection 248 mechanism. The fields are: [5:0] - message length; [12:6] - message 249 pointer; 18:13] - next pointer. */ 250 #define CCM_REG_XX_DESCR_TABLE 0xd0300 251 #define CCM_REG_XX_DESCR_TABLE_SIZE 36 252 /* [R 7] Used to read the value of XX protection Free counter. */ 253 #define CCM_REG_XX_FREE 0xd0184 254 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 255 of the Input Stage XX protection buffer by the XX protection pending 256 messages. Max credit available - 127. Write writes the initial credit 257 value; read returns the current value of the credit counter. Must be 258 initialized to maximum XX protected message size - 2 at start-up. */ 259 #define CCM_REG_XX_INIT_CRD 0xd0220 260 /* [RW 7] The maximum number of pending messages; which may be stored in XX 261 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 262 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 263 counter. */ 264 #define CCM_REG_XX_MSG_NUM 0xd0224 265 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 266 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 267 /* [RW 18] Indirect access to the XX table of the XX protection mechanism. 268 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 269 header pointer. */ 270 #define CCM_REG_XX_TABLE 0xd0280 271 #define CDU_REG_CDU_CHK_MASK0 0x101000 272 #define CDU_REG_CDU_CHK_MASK1 0x101004 273 #define CDU_REG_CDU_CONTROL0 0x101008 274 #define CDU_REG_CDU_DEBUG 0x101010 275 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 276 /* [RW 7] Interrupt mask register #0 read/write */ 277 #define CDU_REG_CDU_INT_MASK 0x10103c 278 /* [R 7] Interrupt register #0 read */ 279 #define CDU_REG_CDU_INT_STS 0x101030 280 /* [RW 5] Parity mask register #0 read/write */ 281 #define CDU_REG_CDU_PRTY_MASK 0x10104c 282 /* [R 5] Parity register #0 read */ 283 #define CDU_REG_CDU_PRTY_STS 0x101040 284 /* [RC 32] logging of error data in case of a CDU load error: 285 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 286 ype_error; ctual_active; ctual_compressed_context}; */ 287 #define CDU_REG_ERROR_DATA 0x101014 288 /* [WB 216] L1TT ram access. each entry has the following format : 289 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 290 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 291 #define CDU_REG_L1TT 0x101800 292 /* [WB 24] MATT ram access. each entry has the following 293 format:{RegionLength[11:0]; egionOffset[11:0]} */ 294 #define CDU_REG_MATT 0x101100 295 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 296 #define CDU_REG_MF_MODE 0x101050 297 /* [R 1] indication the initializing the activity counter by the hardware 298 was done. */ 299 #define CFC_REG_AC_INIT_DONE 0x104078 300 /* [RW 13] activity counter ram access */ 301 #define CFC_REG_ACTIVITY_COUNTER 0x104400 302 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 303 /* [R 1] indication the initializing the cams by the hardware was done. */ 304 #define CFC_REG_CAM_INIT_DONE 0x10407c 305 /* [RW 2] Interrupt mask register #0 read/write */ 306 #define CFC_REG_CFC_INT_MASK 0x104108 307 /* [R 2] Interrupt register #0 read */ 308 #define CFC_REG_CFC_INT_STS 0x1040fc 309 /* [RC 2] Interrupt register #0 read clear */ 310 #define CFC_REG_CFC_INT_STS_CLR 0x104100 311 /* [RW 4] Parity mask register #0 read/write */ 312 #define CFC_REG_CFC_PRTY_MASK 0x104118 313 /* [R 4] Parity register #0 read */ 314 #define CFC_REG_CFC_PRTY_STS 0x10410c 315 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 316 #define CFC_REG_CID_CAM 0x104800 317 #define CFC_REG_CONTROL0 0x104028 318 #define CFC_REG_DEBUG0 0x104050 319 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 320 vector) whether the cfc should be disabled upon it */ 321 #define CFC_REG_DISABLE_ON_ERROR 0x104044 322 /* [RC 14] CFC error vector. when the CFC detects an internal error it will 323 set one of these bits. the bit description can be found in CFC 324 specifications */ 325 #define CFC_REG_ERROR_VECTOR 0x10403c 326 #define CFC_REG_INIT_REG 0x10404c 327 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 328 field allows changing the priorities of the weighted-round-robin arbiter 329 which selects which CFC load client should be served next */ 330 #define CFC_REG_LCREQ_WEIGHTS 0x104084 331 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 332 #define CFC_REG_LINK_LIST 0x104c00 333 #define CFC_REG_LINK_LIST_SIZE 256 334 /* [R 1] indication the initializing the link list by the hardware was done. */ 335 #define CFC_REG_LL_INIT_DONE 0x104074 336 /* [R 9] Number of allocated LCIDs which are at empty state */ 337 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 338 /* [R 9] Number of Arriving LCIDs in Link List Block */ 339 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 340 /* [R 9] Number of Inside LCIDs in Link List Block */ 341 #define CFC_REG_NUM_LCIDS_INSIDE 0x104008 342 /* [R 9] Number of Leaving LCIDs in Link List Block */ 343 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 344 /* [RW 8] The event id for aggregated interrupt 0 */ 345 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038 346 #define CSDM_REG_AGG_INT_EVENT_1 0xc203c 347 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060 348 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064 349 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068 350 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c 351 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070 352 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074 353 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078 354 #define CSDM_REG_AGG_INT_EVENT_17 0xc207c 355 #define CSDM_REG_AGG_INT_EVENT_18 0xc2080 356 #define CSDM_REG_AGG_INT_EVENT_19 0xc2084 357 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040 358 #define CSDM_REG_AGG_INT_EVENT_20 0xc2088 359 #define CSDM_REG_AGG_INT_EVENT_21 0xc208c 360 #define CSDM_REG_AGG_INT_EVENT_22 0xc2090 361 #define CSDM_REG_AGG_INT_EVENT_23 0xc2094 362 #define CSDM_REG_AGG_INT_EVENT_24 0xc2098 363 #define CSDM_REG_AGG_INT_EVENT_25 0xc209c 364 #define CSDM_REG_AGG_INT_EVENT_26 0xc20a0 365 #define CSDM_REG_AGG_INT_EVENT_27 0xc20a4 366 #define CSDM_REG_AGG_INT_EVENT_28 0xc20a8 367 #define CSDM_REG_AGG_INT_EVENT_29 0xc20ac 368 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044 369 #define CSDM_REG_AGG_INT_EVENT_30 0xc20b0 370 #define CSDM_REG_AGG_INT_EVENT_31 0xc20b4 371 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048 372 /* [RW 1] The T bit for aggregated interrupt 0 */ 373 #define CSDM_REG_AGG_INT_T_0 0xc20b8 374 #define CSDM_REG_AGG_INT_T_1 0xc20bc 375 #define CSDM_REG_AGG_INT_T_10 0xc20e0 376 #define CSDM_REG_AGG_INT_T_11 0xc20e4 377 #define CSDM_REG_AGG_INT_T_12 0xc20e8 378 #define CSDM_REG_AGG_INT_T_13 0xc20ec 379 #define CSDM_REG_AGG_INT_T_14 0xc20f0 380 #define CSDM_REG_AGG_INT_T_15 0xc20f4 381 #define CSDM_REG_AGG_INT_T_16 0xc20f8 382 #define CSDM_REG_AGG_INT_T_17 0xc20fc 383 #define CSDM_REG_AGG_INT_T_18 0xc2100 384 #define CSDM_REG_AGG_INT_T_19 0xc2104 385 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 386 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 387 /* [RW 16] The maximum value of the competion counter #0 */ 388 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 389 /* [RW 16] The maximum value of the competion counter #1 */ 390 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 391 /* [RW 16] The maximum value of the competion counter #2 */ 392 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 393 /* [RW 16] The maximum value of the competion counter #3 */ 394 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 395 /* [RW 13] The start address in the internal RAM for the completion 396 counters. */ 397 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 398 /* [RW 32] Interrupt mask register #0 read/write */ 399 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c 400 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 401 /* [R 32] Interrupt register #0 read */ 402 #define CSDM_REG_CSDM_INT_STS_0 0xc2290 403 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 404 /* [RW 11] Parity mask register #0 read/write */ 405 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 406 /* [R 11] Parity register #0 read */ 407 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 408 #define CSDM_REG_ENABLE_IN1 0xc2238 409 #define CSDM_REG_ENABLE_IN2 0xc223c 410 #define CSDM_REG_ENABLE_OUT1 0xc2240 411 #define CSDM_REG_ENABLE_OUT2 0xc2244 412 /* [RW 4] The initial number of messages that can be sent to the pxp control 413 interface without receiving any ACK. */ 414 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 415 /* [ST 32] The number of ACK after placement messages received */ 416 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 417 /* [ST 32] The number of packet end messages received from the parser */ 418 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 419 /* [ST 32] The number of requests received from the pxp async if */ 420 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 421 /* [ST 32] The number of commands received in queue 0 */ 422 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 423 /* [ST 32] The number of commands received in queue 10 */ 424 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 425 /* [ST 32] The number of commands received in queue 11 */ 426 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 427 /* [ST 32] The number of commands received in queue 1 */ 428 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 429 /* [ST 32] The number of commands received in queue 3 */ 430 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 431 /* [ST 32] The number of commands received in queue 4 */ 432 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 433 /* [ST 32] The number of commands received in queue 5 */ 434 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 435 /* [ST 32] The number of commands received in queue 6 */ 436 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 437 /* [ST 32] The number of commands received in queue 7 */ 438 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 439 /* [ST 32] The number of commands received in queue 8 */ 440 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 441 /* [ST 32] The number of commands received in queue 9 */ 442 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 443 /* [RW 13] The start address in the internal RAM for queue counters */ 444 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 445 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 446 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 447 /* [R 1] parser fifo empty in sdm_sync block */ 448 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 449 /* [R 1] parser serial fifo empty in sdm_sync block */ 450 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 451 /* [RW 32] Tick for timer counter. Applicable only when 452 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 453 #define CSDM_REG_TIMER_TICK 0xc2000 454 /* [RW 5] The number of time_slots in the arbitration cycle */ 455 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034 456 /* [RW 3] The source that is associated with arbitration element 0. Source 457 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 458 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 459 #define CSEM_REG_ARB_ELEMENT0 0x200020 460 /* [RW 3] The source that is associated with arbitration element 1. Source 461 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 462 sleeping thread with priority 1; 4- sleeping thread with priority 2. 463 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 464 #define CSEM_REG_ARB_ELEMENT1 0x200024 465 /* [RW 3] The source that is associated with arbitration element 2. Source 466 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 467 sleeping thread with priority 1; 4- sleeping thread with priority 2. 468 Could not be equal to register ~csem_registers_arb_element0.arb_element0 469 and ~csem_registers_arb_element1.arb_element1 */ 470 #define CSEM_REG_ARB_ELEMENT2 0x200028 471 /* [RW 3] The source that is associated with arbitration element 3. Source 472 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 473 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 474 not be equal to register ~csem_registers_arb_element0.arb_element0 and 475 ~csem_registers_arb_element1.arb_element1 and 476 ~csem_registers_arb_element2.arb_element2 */ 477 #define CSEM_REG_ARB_ELEMENT3 0x20002c 478 /* [RW 3] The source that is associated with arbitration element 4. Source 479 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 480 sleeping thread with priority 1; 4- sleeping thread with priority 2. 481 Could not be equal to register ~csem_registers_arb_element0.arb_element0 482 and ~csem_registers_arb_element1.arb_element1 and 483 ~csem_registers_arb_element2.arb_element2 and 484 ~csem_registers_arb_element3.arb_element3 */ 485 #define CSEM_REG_ARB_ELEMENT4 0x200030 486 /* [RW 32] Interrupt mask register #0 read/write */ 487 #define CSEM_REG_CSEM_INT_MASK_0 0x200110 488 #define CSEM_REG_CSEM_INT_MASK_1 0x200120 489 /* [R 32] Interrupt register #0 read */ 490 #define CSEM_REG_CSEM_INT_STS_0 0x200104 491 #define CSEM_REG_CSEM_INT_STS_1 0x200114 492 /* [RW 32] Parity mask register #0 read/write */ 493 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 494 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 495 /* [R 32] Parity register #0 read */ 496 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 497 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 498 #define CSEM_REG_ENABLE_IN 0x2000a4 499 #define CSEM_REG_ENABLE_OUT 0x2000a8 500 /* [RW 32] This address space contains all registers and memories that are 501 placed in SEM_FAST block. The SEM_FAST registers are described in 502 appendix B. In order to access the sem_fast registers the base address 503 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 504 #define CSEM_REG_FAST_MEMORY 0x220000 505 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 506 by the microcode */ 507 #define CSEM_REG_FIC0_DISABLE 0x200224 508 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 509 by the microcode */ 510 #define CSEM_REG_FIC1_DISABLE 0x200234 511 /* [RW 15] Interrupt table Read and write access to it is not possible in 512 the middle of the work */ 513 #define CSEM_REG_INT_TABLE 0x200400 514 /* [ST 24] Statistics register. The number of messages that entered through 515 FIC0 */ 516 #define CSEM_REG_MSG_NUM_FIC0 0x200000 517 /* [ST 24] Statistics register. The number of messages that entered through 518 FIC1 */ 519 #define CSEM_REG_MSG_NUM_FIC1 0x200004 520 /* [ST 24] Statistics register. The number of messages that were sent to 521 FOC0 */ 522 #define CSEM_REG_MSG_NUM_FOC0 0x200008 523 /* [ST 24] Statistics register. The number of messages that were sent to 524 FOC1 */ 525 #define CSEM_REG_MSG_NUM_FOC1 0x20000c 526 /* [ST 24] Statistics register. The number of messages that were sent to 527 FOC2 */ 528 #define CSEM_REG_MSG_NUM_FOC2 0x200010 529 /* [ST 24] Statistics register. The number of messages that were sent to 530 FOC3 */ 531 #define CSEM_REG_MSG_NUM_FOC3 0x200014 532 /* [RW 1] Disables input messages from the passive buffer May be updated 533 during run_time by the microcode */ 534 #define CSEM_REG_PAS_DISABLE 0x20024c 535 /* [WB 128] Debug only. Passive buffer memory */ 536 #define CSEM_REG_PASSIVE_BUFFER 0x202000 537 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 538 #define CSEM_REG_PRAM 0x240000 539 /* [R 16] Valid sleeping threads indication have bit per thread */ 540 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 541 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 542 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 543 /* [RW 16] List of free threads . There is a bit per thread. */ 544 #define CSEM_REG_THREADS_LIST 0x2002e4 545 /* [RW 3] The arbitration scheme of time_slot 0 */ 546 #define CSEM_REG_TS_0_AS 0x200038 547 /* [RW 3] The arbitration scheme of time_slot 10 */ 548 #define CSEM_REG_TS_10_AS 0x200060 549 /* [RW 3] The arbitration scheme of time_slot 11 */ 550 #define CSEM_REG_TS_11_AS 0x200064 551 /* [RW 3] The arbitration scheme of time_slot 12 */ 552 #define CSEM_REG_TS_12_AS 0x200068 553 /* [RW 3] The arbitration scheme of time_slot 13 */ 554 #define CSEM_REG_TS_13_AS 0x20006c 555 /* [RW 3] The arbitration scheme of time_slot 14 */ 556 #define CSEM_REG_TS_14_AS 0x200070 557 /* [RW 3] The arbitration scheme of time_slot 15 */ 558 #define CSEM_REG_TS_15_AS 0x200074 559 /* [RW 3] The arbitration scheme of time_slot 16 */ 560 #define CSEM_REG_TS_16_AS 0x200078 561 /* [RW 3] The arbitration scheme of time_slot 17 */ 562 #define CSEM_REG_TS_17_AS 0x20007c 563 /* [RW 3] The arbitration scheme of time_slot 18 */ 564 #define CSEM_REG_TS_18_AS 0x200080 565 /* [RW 3] The arbitration scheme of time_slot 1 */ 566 #define CSEM_REG_TS_1_AS 0x20003c 567 /* [RW 3] The arbitration scheme of time_slot 2 */ 568 #define CSEM_REG_TS_2_AS 0x200040 569 /* [RW 3] The arbitration scheme of time_slot 3 */ 570 #define CSEM_REG_TS_3_AS 0x200044 571 /* [RW 3] The arbitration scheme of time_slot 4 */ 572 #define CSEM_REG_TS_4_AS 0x200048 573 /* [RW 3] The arbitration scheme of time_slot 5 */ 574 #define CSEM_REG_TS_5_AS 0x20004c 575 /* [RW 3] The arbitration scheme of time_slot 6 */ 576 #define CSEM_REG_TS_6_AS 0x200050 577 /* [RW 3] The arbitration scheme of time_slot 7 */ 578 #define CSEM_REG_TS_7_AS 0x200054 579 /* [RW 3] The arbitration scheme of time_slot 8 */ 580 #define CSEM_REG_TS_8_AS 0x200058 581 /* [RW 3] The arbitration scheme of time_slot 9 */ 582 #define CSEM_REG_TS_9_AS 0x20005c 583 /* [RW 1] Parity mask register #0 read/write */ 584 #define DBG_REG_DBG_PRTY_MASK 0xc0a8 585 /* [R 1] Parity register #0 read */ 586 #define DBG_REG_DBG_PRTY_STS 0xc09c 587 /* [RW 32] Commands memory. The address to command X; row Y is to calculated 588 as 14*X+Y. */ 589 #define DMAE_REG_CMD_MEM 0x102400 590 #define DMAE_REG_CMD_MEM_SIZE 224 591 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 592 initial value is all ones. */ 593 #define DMAE_REG_CRC16C_INIT 0x10201c 594 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 595 CRC-16 T10 initial value is all ones. */ 596 #define DMAE_REG_CRC16T10_INIT 0x102020 597 /* [RW 2] Interrupt mask register #0 read/write */ 598 #define DMAE_REG_DMAE_INT_MASK 0x102054 599 /* [RW 4] Parity mask register #0 read/write */ 600 #define DMAE_REG_DMAE_PRTY_MASK 0x102064 601 /* [R 4] Parity register #0 read */ 602 #define DMAE_REG_DMAE_PRTY_STS 0x102058 603 /* [RW 1] Command 0 go. */ 604 #define DMAE_REG_GO_C0 0x102080 605 /* [RW 1] Command 1 go. */ 606 #define DMAE_REG_GO_C1 0x102084 607 /* [RW 1] Command 10 go. */ 608 #define DMAE_REG_GO_C10 0x102088 609 #define DMAE_REG_GO_C10_SIZE 1 610 /* [RW 1] Command 11 go. */ 611 #define DMAE_REG_GO_C11 0x10208c 612 #define DMAE_REG_GO_C11_SIZE 1 613 /* [RW 1] Command 12 go. */ 614 #define DMAE_REG_GO_C12 0x102090 615 #define DMAE_REG_GO_C12_SIZE 1 616 /* [RW 1] Command 13 go. */ 617 #define DMAE_REG_GO_C13 0x102094 618 #define DMAE_REG_GO_C13_SIZE 1 619 /* [RW 1] Command 14 go. */ 620 #define DMAE_REG_GO_C14 0x102098 621 #define DMAE_REG_GO_C14_SIZE 1 622 /* [RW 1] Command 15 go. */ 623 #define DMAE_REG_GO_C15 0x10209c 624 #define DMAE_REG_GO_C15_SIZE 1 625 /* [RW 1] Command 10 go. */ 626 #define DMAE_REG_GO_C10 0x102088 627 /* [RW 1] Command 11 go. */ 628 #define DMAE_REG_GO_C11 0x10208c 629 /* [RW 1] Command 12 go. */ 630 #define DMAE_REG_GO_C12 0x102090 631 /* [RW 1] Command 13 go. */ 632 #define DMAE_REG_GO_C13 0x102094 633 /* [RW 1] Command 14 go. */ 634 #define DMAE_REG_GO_C14 0x102098 635 /* [RW 1] Command 15 go. */ 636 #define DMAE_REG_GO_C15 0x10209c 637 /* [RW 1] Command 2 go. */ 638 #define DMAE_REG_GO_C2 0x1020a0 639 /* [RW 1] Command 3 go. */ 640 #define DMAE_REG_GO_C3 0x1020a4 641 /* [RW 1] Command 4 go. */ 642 #define DMAE_REG_GO_C4 0x1020a8 643 /* [RW 1] Command 5 go. */ 644 #define DMAE_REG_GO_C5 0x1020ac 645 /* [RW 1] Command 6 go. */ 646 #define DMAE_REG_GO_C6 0x1020b0 647 /* [RW 1] Command 7 go. */ 648 #define DMAE_REG_GO_C7 0x1020b4 649 /* [RW 1] Command 8 go. */ 650 #define DMAE_REG_GO_C8 0x1020b8 651 /* [RW 1] Command 9 go. */ 652 #define DMAE_REG_GO_C9 0x1020bc 653 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 654 input is disregarded; valid is deasserted; all other signals are treated 655 as usual; if 1 - normal activity. */ 656 #define DMAE_REG_GRC_IFEN 0x102008 657 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 658 acknowledge input is disregarded; valid is deasserted; full is asserted; 659 all other signals are treated as usual; if 1 - normal activity. */ 660 #define DMAE_REG_PCI_IFEN 0x102004 661 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 662 initial value to the credit counter; related to the address. Read returns 663 the current value of the counter. */ 664 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 665 /* [RW 8] Aggregation command. */ 666 #define DORQ_REG_AGG_CMD0 0x170060 667 /* [RW 8] Aggregation command. */ 668 #define DORQ_REG_AGG_CMD1 0x170064 669 /* [RW 8] Aggregation command. */ 670 #define DORQ_REG_AGG_CMD2 0x170068 671 /* [RW 8] Aggregation command. */ 672 #define DORQ_REG_AGG_CMD3 0x17006c 673 /* [RW 28] UCM Header. */ 674 #define DORQ_REG_CMHEAD_RX 0x170050 675 /* [RW 32] Doorbell address for RBC doorbells (function 0). */ 676 #define DORQ_REG_DB_ADDR0 0x17008c 677 /* [RW 5] Interrupt mask register #0 read/write */ 678 #define DORQ_REG_DORQ_INT_MASK 0x170180 679 /* [R 5] Interrupt register #0 read */ 680 #define DORQ_REG_DORQ_INT_STS 0x170174 681 /* [RC 5] Interrupt register #0 read clear */ 682 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 683 /* [RW 2] Parity mask register #0 read/write */ 684 #define DORQ_REG_DORQ_PRTY_MASK 0x170190 685 /* [R 2] Parity register #0 read */ 686 #define DORQ_REG_DORQ_PRTY_STS 0x170184 687 /* [RW 8] The address to write the DPM CID to STORM. */ 688 #define DORQ_REG_DPM_CID_ADDR 0x170044 689 /* [RW 5] The DPM mode CID extraction offset. */ 690 #define DORQ_REG_DPM_CID_OFST 0x170030 691 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 692 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 693 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 694 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 695 /* [R 13] Current value of the DQ FIFO fill level according to following 696 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 697 doorbell. */ 698 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 699 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 700 equal to full threshold; reset on full clear. */ 701 #define DORQ_REG_DQ_FULL_ST 0x1700c0 702 /* [RW 28] The value sent to CM header in the case of CFC load error. */ 703 #define DORQ_REG_ERR_CMHEAD 0x170058 704 #define DORQ_REG_IF_EN 0x170004 705 #define DORQ_REG_MODE_ACT 0x170008 706 /* [RW 5] The normal mode CID extraction offset. */ 707 #define DORQ_REG_NORM_CID_OFST 0x17002c 708 /* [RW 28] TCM Header when only TCP context is loaded. */ 709 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c 710 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch 711 Interface. */ 712 #define DORQ_REG_OUTST_REQ 0x17003c 713 #define DORQ_REG_REGN 0x170038 714 /* [R 4] Current value of response A counter credit. Initial credit is 715 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 716 register. */ 717 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac 718 /* [R 4] Current value of response B counter credit. Initial credit is 719 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 720 register. */ 721 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 722 /* [RW 4] The initial credit at the Doorbell Response Interface. The write 723 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 724 read reads this written value. */ 725 #define DORQ_REG_RSP_INIT_CRD 0x170048 726 /* [RW 4] Initial activity counter value on the load request; when the 727 shortcut is done. */ 728 #define DORQ_REG_SHRT_ACT_CNT 0x170070 729 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 730 #define DORQ_REG_SHRT_CMHEAD 0x170054 731 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 732 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 733 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 734 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 735 #define HC_REG_AGG_INT_0 0x108050 736 #define HC_REG_AGG_INT_1 0x108054 737 #define HC_REG_ATTN_BIT 0x108120 738 #define HC_REG_ATTN_IDX 0x108100 739 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 740 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 741 #define HC_REG_ATTN_NUM_P0 0x108038 742 #define HC_REG_ATTN_NUM_P1 0x10803c 743 #define HC_REG_COMMAND_REG 0x108180 744 #define HC_REG_CONFIG_0 0x108000 745 #define HC_REG_CONFIG_1 0x108004 746 #define HC_REG_FUNC_NUM_P0 0x1080ac 747 #define HC_REG_FUNC_NUM_P1 0x1080b0 748 /* [RW 3] Parity mask register #0 read/write */ 749 #define HC_REG_HC_PRTY_MASK 0x1080a0 750 /* [R 3] Parity register #0 read */ 751 #define HC_REG_HC_PRTY_STS 0x108094 752 #define HC_REG_INT_MASK 0x108108 753 #define HC_REG_LEADING_EDGE_0 0x108040 754 #define HC_REG_LEADING_EDGE_1 0x108048 755 #define HC_REG_P0_PROD_CONS 0x108200 756 #define HC_REG_P1_PROD_CONS 0x108400 757 #define HC_REG_PBA_COMMAND 0x108140 758 #define HC_REG_PCI_CONFIG_0 0x108010 759 #define HC_REG_PCI_CONFIG_1 0x108014 760 #define HC_REG_STATISTIC_COUNTERS 0x109000 761 #define HC_REG_TRAILING_EDGE_0 0x108044 762 #define HC_REG_TRAILING_EDGE_1 0x10804c 763 #define HC_REG_UC_RAM_ADDR_0 0x108028 764 #define HC_REG_UC_RAM_ADDR_1 0x108030 765 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 766 #define HC_REG_VQID_0 0x108008 767 #define HC_REG_VQID_1 0x10800c 768 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 769 #define MCP_REG_MCPR_NVM_ADDR 0x8640c 770 #define MCP_REG_MCPR_NVM_CFG4 0x8642c 771 #define MCP_REG_MCPR_NVM_COMMAND 0x86400 772 #define MCP_REG_MCPR_NVM_READ 0x86410 773 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 774 #define MCP_REG_MCPR_NVM_WRITE 0x86408 775 #define MCP_REG_MCPR_NVM_WRITE1 0x86428 776 #define MCP_REG_MCPR_SCRATCH 0xa0000 777 /* [R 32] read first 32 bit after inversion of function 0. mapped as 778 follows: [0] NIG attention for function0; [1] NIG attention for 779 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 780 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 781 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 782 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 783 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 784 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 785 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 786 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 787 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 788 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 789 Parity error; [31] PBF Hw interrupt; */ 790 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 791 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 792 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 793 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 794 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 795 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 796 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 797 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 798 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 799 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 800 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 801 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 802 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 803 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 804 interrupt; */ 805 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 806 /* [R 32] read second 32 bit after inversion of function 0. mapped as 807 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 808 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 809 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 810 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 811 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 812 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 813 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 814 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 815 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 816 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 817 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 818 interrupt; */ 819 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 820 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 821 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 822 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 823 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 824 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 825 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 826 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 827 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 828 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 829 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 830 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 831 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 832 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 833 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 834 /* [R 32] read third 32 bit after inversion of function 0. mapped as 835 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 836 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 837 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 838 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 839 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 840 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 841 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 842 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 843 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 844 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 845 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 846 attn1; */ 847 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 848 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 849 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 850 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 851 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 852 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 853 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 854 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 855 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 856 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 857 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 858 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 859 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 860 timers attn_4 func1; [30] General attn0; [31] General attn1; */ 861 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 862 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as 863 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 864 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 865 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 866 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 867 [14] General attn16; [15] General attn17; [16] General attn18; [17] 868 General attn19; [18] General attn20; [19] General attn21; [20] Main power 869 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 870 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 871 Latched timeout attention; [27] GRC Latched reserved access attention; 872 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 873 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 874 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 875 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 876 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 877 General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 878 [4] General attn6; [5] General attn7; [6] General attn8; [7] General 879 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 880 General attn13; [12] General attn14; [13] General attn15; [14] General 881 attn16; [15] General attn17; [16] General attn18; [17] General attn19; 882 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 883 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 884 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 885 attention; [27] GRC Latched reserved access attention; [28] MCP Latched 886 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 887 ump_tx_parity; [31] MCP Latched scpad_parity; */ 888 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 889 /* [W 14] write to this register results with the clear of the latched 890 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 891 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 892 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 893 GRC Latched reserved access attention; one in d7 clears Latched 894 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 895 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 896 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 897 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 898 from this register return zero */ 899 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 900 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped 901 as follows: [0] NIG attention for function0; [1] NIG attention for 902 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 903 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 904 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 905 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 906 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 907 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 908 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 909 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 910 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 911 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 912 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 913 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 914 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 915 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 916 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 917 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 918 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 919 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 920 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped 921 as follows: [0] NIG attention for function0; [1] NIG attention for 922 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 923 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 924 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 925 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 926 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 927 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 928 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 929 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 930 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 931 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 932 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 933 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 934 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 935 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 936 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 937 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 938 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 939 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 940 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped 941 as follows: [0] NIG attention for function0; [1] NIG attention for 942 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 943 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 944 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 945 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 946 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 947 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 948 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 949 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 950 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 951 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 952 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 953 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 954 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 955 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 956 as follows: [0] NIG attention for function0; [1] NIG attention for 957 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 958 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 959 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 960 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 961 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 962 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 963 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 964 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 965 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 966 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 967 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 968 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 969 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 970 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped 971 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 972 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 973 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 974 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 975 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 976 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 977 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 978 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 979 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 980 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 981 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 982 interrupt; */ 983 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 984 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 985 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped 986 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 987 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 988 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 989 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 990 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 991 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 992 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 993 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 994 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 995 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 996 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 997 interrupt; */ 998 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 999 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1000 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1001 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1002 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1003 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1004 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1005 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1006 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1007 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1008 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1009 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1010 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1011 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1012 interrupt; */ 1013 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1014 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1015 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1016 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1017 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1018 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1019 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1020 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1021 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1022 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1023 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1024 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1025 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1026 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1027 interrupt; */ 1028 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1029 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1030 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1031 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1032 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1033 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1034 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1035 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1036 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1037 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1038 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1039 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1040 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1041 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1042 attn1; */ 1043 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1044 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1045 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1046 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1047 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1048 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1049 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1050 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1051 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1052 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1053 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1054 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1055 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1056 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1057 attn1; */ 1058 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1059 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1060 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1061 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1062 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1063 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1064 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1065 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1066 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1067 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1068 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1069 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1070 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1071 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1072 attn1; */ 1073 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1074 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1075 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1076 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1077 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1078 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1079 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1080 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1081 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1082 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1083 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1084 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1085 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1086 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1087 attn1; */ 1088 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1089 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1090 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1091 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1092 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1093 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1094 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1095 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1096 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1097 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1098 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1099 Latched timeout attention; [27] GRC Latched reserved access attention; 1100 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1101 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1102 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1103 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1104 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1105 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1106 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1107 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1108 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1109 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1110 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1111 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1112 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1113 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1114 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1115 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1116 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1117 Latched timeout attention; [27] GRC Latched reserved access attention; 1118 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1119 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1120 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1121 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1122 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1123 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1124 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1125 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1126 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1127 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1128 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1129 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1130 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1131 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1132 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1133 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1134 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1135 Latched timeout attention; [27] GRC Latched reserved access attention; 1136 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1137 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1138 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1139 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1140 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1141 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1142 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1143 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1144 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1145 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1146 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1147 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1148 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1149 Latched timeout attention; [27] GRC Latched reserved access attention; 1150 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1151 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1152 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1153 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1154 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1155 128 bit vector */ 1156 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1157 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1158 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1159 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1160 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1161 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034 1162 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038 1163 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c 1164 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040 1165 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044 1166 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048 1167 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c 1168 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1169 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1170 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1171 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1172 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 1173 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 1174 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1175 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1176 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1177 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1178 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1179 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1180 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1181 #define MISC_REG_AEU_GENERAL_MASK 0xa61c 1182 /* [RW 32] first 32b for inverting the input for function 0; for each bit: 1183 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1184 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1185 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1186 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1187 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1188 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1189 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1190 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1191 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1192 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1193 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1194 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1195 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1196 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1197 /* [RW 32] second 32b for inverting the input for function 0; for each bit: 1198 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1199 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1200 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1201 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1202 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1203 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1204 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1205 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1206 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1207 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1208 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1209 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1210 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1211 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1212 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1213 [9:8] = raserved. Zero = mask; one = unmask */ 1214 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1215 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1216 /* [RW 1] If set a system kill occurred */ 1217 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1218 /* [RW 32] Represent the status of the input vector to the AEU when a system 1219 kill occurred. The register is reset in por reset. Mapped as follows: [0] 1220 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1221 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1222 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1223 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1224 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1225 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1226 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1227 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1228 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1229 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1230 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1231 interrupt; */ 1232 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1233 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1234 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1235 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1236 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1237 Port. */ 1238 #define MISC_REG_BOND_ID 0xa400 1239 /* [R 8] These bits indicate the metal revision of the chip. This value 1240 starts at 0x00 for each all-layer tape-out and increments by one for each 1241 tape-out. */ 1242 #define MISC_REG_CHIP_METAL 0xa404 1243 /* [R 16] These bits indicate the part number for the chip. */ 1244 #define MISC_REG_CHIP_NUM 0xa408 1245 /* [R 4] These bits indicate the base revision of the chip. This value 1246 starts at 0x0 for the A0 tape-out and increments by one for each 1247 all-layer tape-out. */ 1248 #define MISC_REG_CHIP_REV 0xa40c 1249 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1250 32 clients. Each client can be controlled by one driver only. One in each 1251 bit represent that this driver control the appropriate client (Ex: bit 5 1252 is set means this driver control client number 5). addr1 = set; addr0 = 1253 clear; read from both addresses will give the same result = status. write 1254 to address 1 will set a request to control all the clients that their 1255 appropriate bit (in the write command) is set. if the client is free (the 1256 appropriate bit in all the other drivers is clear) one will be written to 1257 that driver register; if the client isn't free the bit will remain zero. 1258 if the appropriate bit is set (the driver request to gain control on a 1259 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1260 interrupt will be asserted). write to address 0 will set a request to 1261 free all the clients that their appropriate bit (in the write command) is 1262 set. if the appropriate bit is clear (the driver request to free a client 1263 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1264 be asserted). */ 1265 #define MISC_REG_DRIVER_CONTROL_10 0xa3e0 1266 #define MISC_REG_DRIVER_CONTROL_10_SIZE 2 1267 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1268 32 clients. Each client can be controlled by one driver only. One in each 1269 bit represent that this driver control the appropriate client (Ex: bit 5 1270 is set means this driver control client number 5). addr1 = set; addr0 = 1271 clear; read from both addresses will give the same result = status. write 1272 to address 1 will set a request to control all the clients that their 1273 appropriate bit (in the write command) is set. if the client is free (the 1274 appropriate bit in all the other drivers is clear) one will be written to 1275 that driver register; if the client isn't free the bit will remain zero. 1276 if the appropriate bit is set (the driver request to gain control on a 1277 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1278 interrupt will be asserted). write to address 0 will set a request to 1279 free all the clients that their appropriate bit (in the write command) is 1280 set. if the appropriate bit is clear (the driver request to free a client 1281 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1282 be asserted). */ 1283 #define MISC_REG_DRIVER_CONTROL_11 0xa3e8 1284 #define MISC_REG_DRIVER_CONTROL_11_SIZE 2 1285 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1286 32 clients. Each client can be controlled by one driver only. One in each 1287 bit represent that this driver control the appropriate client (Ex: bit 5 1288 is set means this driver control client number 5). addr1 = set; addr0 = 1289 clear; read from both addresses will give the same result = status. write 1290 to address 1 will set a request to control all the clients that their 1291 appropriate bit (in the write command) is set. if the client is free (the 1292 appropriate bit in all the other drivers is clear) one will be written to 1293 that driver register; if the client isn't free the bit will remain zero. 1294 if the appropriate bit is set (the driver request to gain control on a 1295 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1296 interrupt will be asserted). write to address 0 will set a request to 1297 free all the clients that their appropriate bit (in the write command) is 1298 set. if the appropriate bit is clear (the driver request to free a client 1299 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1300 be asserted). */ 1301 #define MISC_REG_DRIVER_CONTROL_12 0xa3f0 1302 #define MISC_REG_DRIVER_CONTROL_12_SIZE 2 1303 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1304 32 clients. Each client can be controlled by one driver only. One in each 1305 bit represent that this driver control the appropriate client (Ex: bit 5 1306 is set means this driver control client number 5). addr1 = set; addr0 = 1307 clear; read from both addresses will give the same result = status. write 1308 to address 1 will set a request to control all the clients that their 1309 appropriate bit (in the write command) is set. if the client is free (the 1310 appropriate bit in all the other drivers is clear) one will be written to 1311 that driver register; if the client isn't free the bit will remain zero. 1312 if the appropriate bit is set (the driver request to gain control on a 1313 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1314 interrupt will be asserted). write to address 0 will set a request to 1315 free all the clients that their appropriate bit (in the write command) is 1316 set. if the appropriate bit is clear (the driver request to free a client 1317 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1318 be asserted). */ 1319 #define MISC_REG_DRIVER_CONTROL_13 0xa3f8 1320 #define MISC_REG_DRIVER_CONTROL_13_SIZE 2 1321 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1322 32 clients. Each client can be controlled by one driver only. One in each 1323 bit represent that this driver control the appropriate client (Ex: bit 5 1324 is set means this driver control client number 5). addr1 = set; addr0 = 1325 clear; read from both addresses will give the same result = status. write 1326 to address 1 will set a request to control all the clients that their 1327 appropriate bit (in the write command) is set. if the client is free (the 1328 appropriate bit in all the other drivers is clear) one will be written to 1329 that driver register; if the client isn't free the bit will remain zero. 1330 if the appropriate bit is set (the driver request to gain control on a 1331 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1332 interrupt will be asserted). write to address 0 will set a request to 1333 free all the clients that their appropriate bit (in the write command) is 1334 set. if the appropriate bit is clear (the driver request to free a client 1335 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1336 be asserted). */ 1337 #define MISC_REG_DRIVER_CONTROL_1 0xa510 1338 #define MISC_REG_DRIVER_CONTROL_14 0xa5e0 1339 #define MISC_REG_DRIVER_CONTROL_14_SIZE 2 1340 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1341 32 clients. Each client can be controlled by one driver only. One in each 1342 bit represent that this driver control the appropriate client (Ex: bit 5 1343 is set means this driver control client number 5). addr1 = set; addr0 = 1344 clear; read from both addresses will give the same result = status. write 1345 to address 1 will set a request to control all the clients that their 1346 appropriate bit (in the write command) is set. if the client is free (the 1347 appropriate bit in all the other drivers is clear) one will be written to 1348 that driver register; if the client isn't free the bit will remain zero. 1349 if the appropriate bit is set (the driver request to gain control on a 1350 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1351 interrupt will be asserted). write to address 0 will set a request to 1352 free all the clients that their appropriate bit (in the write command) is 1353 set. if the appropriate bit is clear (the driver request to free a client 1354 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1355 be asserted). */ 1356 #define MISC_REG_DRIVER_CONTROL_15 0xa5e8 1357 #define MISC_REG_DRIVER_CONTROL_15_SIZE 2 1358 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1359 32 clients. Each client can be controlled by one driver only. One in each 1360 bit represent that this driver control the appropriate client (Ex: bit 5 1361 is set means this driver control client number 5). addr1 = set; addr0 = 1362 clear; read from both addresses will give the same result = status. write 1363 to address 1 will set a request to control all the clients that their 1364 appropriate bit (in the write command) is set. if the client is free (the 1365 appropriate bit in all the other drivers is clear) one will be written to 1366 that driver register; if the client isn't free the bit will remain zero. 1367 if the appropriate bit is set (the driver request to gain control on a 1368 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1369 interrupt will be asserted). write to address 0 will set a request to 1370 free all the clients that their appropriate bit (in the write command) is 1371 set. if the appropriate bit is clear (the driver request to free a client 1372 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1373 be asserted). */ 1374 #define MISC_REG_DRIVER_CONTROL_16 0xa5f0 1375 #define MISC_REG_DRIVER_CONTROL_16_SIZE 2 1376 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 1377 32 clients. Each client can be controlled by one driver only. One in each 1378 bit represent that this driver control the appropriate client (Ex: bit 5 1379 is set means this driver control client number 5). addr1 = set; addr0 = 1380 clear; read from both addresses will give the same result = status. write 1381 to address 1 will set a request to control all the clients that their 1382 appropriate bit (in the write command) is set. if the client is free (the 1383 appropriate bit in all the other drivers is clear) one will be written to 1384 that driver register; if the client isn't free the bit will remain zero. 1385 if the appropriate bit is set (the driver request to gain control on a 1386 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1387 interrupt will be asserted). write to address 0 will set a request to 1388 free all the clients that their appropriate bit (in the write command) is 1389 set. if the appropriate bit is clear (the driver request to free a client 1390 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1391 be asserted). */ 1392 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1393 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1394 only. */ 1395 #define MISC_REG_E1HMF_MODE 0xa5f8 1396 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1397 these bits is written as a '1'; the corresponding SPIO bit will turn off 1398 it's drivers and become an input. This is the reset state of all GPIO 1399 pins. The read value of these bits will be a '1' if that last command 1400 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1401 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1402 as a '1'; the corresponding GPIO bit will drive low. The read value of 1403 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1404 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1405 SET When any of these bits is written as a '1'; the corresponding GPIO 1406 bit will drive high (if it has that capability). The read value of these 1407 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1408 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1409 RO; These bits indicate the read value of each of the eight GPIO pins. 1410 This is the result value of the pin; not the drive value. Writing these 1411 bits will have not effect. */ 1412 #define MISC_REG_GPIO 0xa490 1413 /* [R 28] this field hold the last information that caused reserved 1414 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1415 [27:24] the master that caused the attention - according to the following 1416 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1417 dbu; 8 = dmae */ 1418 #define MISC_REG_GRC_RSV_ATTN 0xa3c0 1419 /* [R 28] this field hold the last information that caused timeout 1420 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1421 [27:24] the master that caused the attention - according to the following 1422 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1423 dbu; 8 = dmae */ 1424 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1425 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1426 access that does not finish within 1427 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1428 cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1429 assert it attention output. */ 1430 #define MISC_REG_GRC_TIMEOUT_EN 0xa280 1431 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1432 the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1433 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1434 (reset value 001) Charge pump current control; 111 for 720u; 011 for 1435 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1436 Global bias control; When bit 7 is high bias current will be 10 0gh; When 1437 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1438 Pll_observe (reset value 010) Bits to control observability. bit 10 is 1439 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1440 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1441 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1442 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1443 internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1444 connected to RESET input directly. [15] capRetry_en (reset value 0) 1445 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1446 value 0) bit to continuously monitor vco freq (inverted). [17] 1447 freqDetRestart_en (reset value 0) bit to enable restart when not freq 1448 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1449 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1450 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1451 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1452 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1453 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1454 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1455 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1456 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1457 restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1458 register bits. */ 1459 #define MISC_REG_LCPLL_CTRL_1 0xa2a4 1460 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1461 /* [RW 4] Interrupt mask register #0 read/write */ 1462 #define MISC_REG_MISC_INT_MASK 0xa388 1463 /* [RW 1] Parity mask register #0 read/write */ 1464 #define MISC_REG_MISC_PRTY_MASK 0xa398 1465 /* [R 1] Parity register #0 read */ 1466 #define MISC_REG_MISC_PRTY_STS 0xa38c 1467 #define MISC_REG_NIG_WOL_P0 0xa270 1468 #define MISC_REG_NIG_WOL_P1 0xa274 1469 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1470 assertion */ 1471 #define MISC_REG_PCIE_HOT_RESET 0xa618 1472 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1473 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1474 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1475 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1476 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1477 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1478 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1479 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1480 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1481 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1482 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1483 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1484 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1485 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1486 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1487 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1488 testa_en (reset value 0); */ 1489 #define MISC_REG_PLL_STORM_CTRL_1 0xa294 1490 #define MISC_REG_PLL_STORM_CTRL_2 0xa298 1491 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1492 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1493 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1494 write/read zero = the specific block is in reset; addr 0-wr- the write 1495 value will be written to the register; addr 1-set - one will be written 1496 to all the bits that have the value of one in the data written (bits that 1497 have the value of zero will not be change) ; addr 2-clear - zero will be 1498 written to all the bits that have the value of one in the data written 1499 (bits that have the value of zero will not be change); addr 3-ignore; 1500 read ignore from all addr except addr 00; inside order of the bits is: 1501 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1502 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1503 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1504 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1505 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1506 rst_pxp_rq_rd_wr; 31:17] reserved */ 1507 #define MISC_REG_RESET_REG_2 0xa590 1508 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1509 shared with the driver resides */ 1510 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1511 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1512 the corresponding SPIO bit will turn off it's drivers and become an 1513 input. This is the reset state of all SPIO pins. The read value of these 1514 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1515 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1516 is written as a '1'; the corresponding SPIO bit will drive low. The read 1517 value of these bits will be a '1' if that last command (#SET; #CLR; or 1518 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1519 these bits is written as a '1'; the corresponding SPIO bit will drive 1520 high (if it has that capability). The read value of these bits will be a 1521 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1522 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1523 each of the eight SPIO pins. This is the result value of the pin; not the 1524 drive value. Writing these bits will have not effect. Each 8 bits field 1525 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1526 from VAUX. (This is an output pin only; the FLOAT field is not applicable 1527 for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1528 VAUX. (This is an output pin only; FLOAT field is not applicable for this 1529 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1530 select VAUX supply. (This is an output pin only; it is not controlled by 1531 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1532 field is not applicable for this pin; only the VALUE fields is relevant - 1533 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1534 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1535 device ID select; read by UMP firmware. */ 1536 #define MISC_REG_SPIO 0xa4fc 1537 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1538 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1539 [7:0] reserved */ 1540 #define MISC_REG_SPIO_EVENT_EN 0xa2b8 1541 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1542 corresponding bit in the #OLD_VALUE register. This will acknowledge an 1543 interrupt on the falling edge of corresponding SPIO input (reset value 1544 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1545 in the #OLD_VALUE register. This will acknowledge an interrupt on the 1546 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1547 RO; These bits indicate the old value of the SPIO input value. When the 1548 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1549 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1550 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1551 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1552 RO; These bits indicate the current SPIO interrupt state for each SPIO 1553 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1554 command bit is written. This bit is set when the SPIO input does not 1555 match the current value in #OLD_VALUE (reset value 0). */ 1556 #define MISC_REG_SPIO_INT 0xa500 1557 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1558 loaded; 0-prepare; -unprepare */ 1559 #define MISC_REG_UNPREPARED 0xa424 1560 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1561 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1562 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1563 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1564 /* [RW 1] Input enable for RX_BMAC0 IF */ 1565 #define NIG_REG_BMAC0_IN_EN 0x100ac 1566 /* [RW 1] output enable for TX_BMAC0 IF */ 1567 #define NIG_REG_BMAC0_OUT_EN 0x100e0 1568 /* [RW 1] output enable for TX BMAC pause port 0 IF */ 1569 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1570 /* [RW 1] output enable for RX_BMAC0_REGS IF */ 1571 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1572 /* [RW 1] output enable for RX BRB1 port0 IF */ 1573 #define NIG_REG_BRB0_OUT_EN 0x100f8 1574 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1575 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1576 /* [RW 1] output enable for RX BRB1 port1 IF */ 1577 #define NIG_REG_BRB1_OUT_EN 0x100fc 1578 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1579 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1580 /* [RW 1] output enable for RX BRB1 LP IF */ 1581 #define NIG_REG_BRB_LB_OUT_EN 0x10100 1582 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1583 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1584 72:73]-vnic_num; 81:74]-sideband_info */ 1585 #define NIG_REG_DEBUG_PACKET_LB 0x10800 1586 /* [RW 1] Input enable for TX Debug packet */ 1587 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1588 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1589 packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1590 First packet may be deleted from the middle. And last packet will be 1591 always deleted till the end. */ 1592 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1593 /* [RW 1] Output enable to EMAC0 */ 1594 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1595 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1596 to emac for port0; other way to bmac for port0 */ 1597 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1598 /* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */ 1599 #define NIG_REG_EGRESS_MNG0_FIFO 0x1045c 1600 /* [RW 1] Input enable for TX PBF user packet port0 IF */ 1601 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1602 /* [RW 1] Input enable for TX PBF user packet port1 IF */ 1603 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1604 /* [RW 1] Input enable for RX_EMAC0 IF */ 1605 #define NIG_REG_EMAC0_IN_EN 0x100a4 1606 /* [RW 1] output enable for TX EMAC pause port 0 IF */ 1607 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1608 /* [R 1] status from emac0. This bit is set when MDINT from either the 1609 EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1610 be cleared in the attached PHY device that is driving the MINT pin. */ 1611 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1612 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1613 are described in appendix A. In order to access the BMAC0 registers; the 1614 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1615 added to each BMAC register offset */ 1616 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1617 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1618 are described in appendix A. In order to access the BMAC0 registers; the 1619 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1620 added to each BMAC register offset */ 1621 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1622 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1623 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1624 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1625 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 1626 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1627 /* [RW 1] led 10g for port 0 */ 1628 #define NIG_REG_LED_10G_P0 0x10320 1629 /* [RW 1] led 10g for port 1 */ 1630 #define NIG_REG_LED_10G_P1 0x10324 1631 /* [RW 1] Port0: This bit is set to enable the use of the 1632 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1633 defined below. If this bit is cleared; then the blink rate will be about 1634 8Hz. */ 1635 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 1636 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 1637 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 1638 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 1639 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1640 /* [RW 1] Port0: If set along with the 1641 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 1642 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1643 bit; the Traffic LED will blink with the blink rate specified in 1644 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1645 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1646 fields. */ 1647 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 1648 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 1649 Traffic LED will then be controlled via bit ~nig_registers_ 1650 led_control_traffic_p0.led_control_traffic_p0 and bit 1651 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 1652 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 1653 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 1654 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 1655 set; the LED will blink with blink rate specified in 1656 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1657 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1658 fields. */ 1659 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 1660 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1661 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1662 #define NIG_REG_LED_MODE_P0 0x102f0 1663 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 1664 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 1665 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1666 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 1667 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1668 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1669 /* [RW 2] Determine the classification participants. 0: no classification.1: 1670 classification upon VLAN id. 2: classification upon MAC address. 3: 1671 classification upon both VLAN id & MAC addr. */ 1672 #define NIG_REG_LLH0_CLS_TYPE 0x16080 1673 /* [RW 32] cm header for llh0 */ 1674 #define NIG_REG_LLH0_CM_HEADER 0x1007c 1675 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 1676 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 1677 /* [RW 16] destination TCP address 1. The LLH will look for this address in 1678 all incoming packets. */ 1679 #define NIG_REG_LLH0_DEST_TCP_0 0x10220 1680 /* [RW 16] destination UDP address 1 The LLH will look for this address in 1681 all incoming packets. */ 1682 #define NIG_REG_LLH0_DEST_UDP_0 0x10214 1683 #define NIG_REG_LLH0_ERROR_MASK 0x1008c 1684 /* [RW 8] event id for llh0 */ 1685 #define NIG_REG_LLH0_EVENT_ID 0x10084 1686 #define NIG_REG_LLH0_FUNC_EN 0x160fc 1687 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 1688 /* [RW 1] Determine the IP version to look for in 1689 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 1690 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 1691 /* [RW 1] t bit for llh0 */ 1692 #define NIG_REG_LLH0_T_BIT 0x10074 1693 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 1694 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c 1695 /* [RW 8] init credit counter for port0 in LLH */ 1696 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1697 #define NIG_REG_LLH0_XCM_MASK 0x10130 1698 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 1699 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1700 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1701 /* [RW 2] Determine the classification participants. 0: no classification.1: 1702 classification upon VLAN id. 2: classification upon MAC address. 3: 1703 classification upon both VLAN id & MAC addr. */ 1704 #define NIG_REG_LLH1_CLS_TYPE 0x16084 1705 /* [RW 32] cm header for llh1 */ 1706 #define NIG_REG_LLH1_CM_HEADER 0x10080 1707 #define NIG_REG_LLH1_ERROR_MASK 0x10090 1708 /* [RW 8] event id for llh1 */ 1709 #define NIG_REG_LLH1_EVENT_ID 0x10088 1710 /* [RW 8] init credit counter for port1 in LLH */ 1711 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1712 #define NIG_REG_LLH1_XCM_MASK 0x10134 1713 /* [RW 1] When this bit is set; the LLH will expect all packets to be with 1714 e1hov */ 1715 #define NIG_REG_LLH_E1HOV_MODE 0x160d8 1716 /* [RW 1] When this bit is set; the LLH will classify the packet before 1717 sending it to the BRB or calculating WoL on it. */ 1718 #define NIG_REG_LLH_MF_MODE 0x16024 1719 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1720 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1721 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1722 #define NIG_REG_NIG_EMAC0_EN 0x1003c 1723 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 1724 #define NIG_REG_NIG_EMAC1_EN 0x10040 1725 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 1726 EMAC0 to strip the CRC from the ingress packets. */ 1727 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1728 /* [R 32] Interrupt register #0 read */ 1729 #define NIG_REG_NIG_INT_STS_0 0x103b0 1730 #define NIG_REG_NIG_INT_STS_1 0x103c0 1731 /* [R 32] Parity register #0 read */ 1732 #define NIG_REG_NIG_PRTY_STS 0x103d0 1733 /* [RW 1] Input enable for RX PBF LP IF */ 1734 #define NIG_REG_PBF_LB_IN_EN 0x100b4 1735 /* [RW 1] Value of this register will be transmitted to port swap when 1736 ~nig_registers_strap_override.strap_override =1 */ 1737 #define NIG_REG_PORT_SWAP 0x10394 1738 /* [RW 1] output enable for RX parser descriptor IF */ 1739 #define NIG_REG_PRS_EOP_OUT_EN 0x10104 1740 /* [RW 1] Input enable for RX parser request IF */ 1741 #define NIG_REG_PRS_REQ_IN_EN 0x100b8 1742 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 1743 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 1744 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 1745 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 1746 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1747 for port0 */ 1748 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 1749 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 1750 for port0 */ 1751 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 1752 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 1753 between 1024 and 1522 bytes for port0 */ 1754 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 1755 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 1756 between 1523 bytes and above for port0 */ 1757 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 1758 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 1759 for port1 */ 1760 #define NIG_REG_STAT1_BRB_DISCARD 0x10628 1761 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 1762 between 1024 and 1522 bytes for port1 */ 1763 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 1764 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 1765 between 1523 bytes and above for port1 */ 1766 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 1767 /* [WB_R 64] Rx statistics : User octets received for LP */ 1768 #define NIG_REG_STAT2_BRB_OCTET 0x107e0 1769 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 1770 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 1771 /* [RW 1] port swap mux selection. If this register equal to 0 then port 1772 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 1773 ort swap is equal to ~nig_registers_port_swap.port_swap */ 1774 #define NIG_REG_STRAP_OVERRIDE 0x10398 1775 /* [RW 1] output enable for RX_XCM0 IF */ 1776 #define NIG_REG_XCM0_OUT_EN 0x100f0 1777 /* [RW 1] output enable for RX_XCM1 IF */ 1778 #define NIG_REG_XCM1_OUT_EN 0x100f4 1779 /* [RW 1] control to xgxs - remote PHY in-band MDIO */ 1780 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 1781 /* [RW 5] control to xgxs - CL45 DEVAD */ 1782 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 1783 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 1784 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 1785 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 1786 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 1787 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 1788 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 1789 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 1790 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 1791 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 1792 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 1793 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 1794 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 1795 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 1796 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 1797 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 1798 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 1799 /* [RW 1] Disable processing further tasks from port 0 (after ending the 1800 current task in process). */ 1801 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 1802 /* [RW 1] Disable processing further tasks from port 1 (after ending the 1803 current task in process). */ 1804 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 1805 /* [RW 1] Disable processing further tasks from port 4 (after ending the 1806 current task in process). */ 1807 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 1808 #define PBF_REG_IF_ENABLE_REG 0x140044 1809 /* [RW 1] Init bit. When set the initial credits are copied to the credit 1810 registers (except the port credits). Should be set and then reset after 1811 the configuration of the block has ended. */ 1812 #define PBF_REG_INIT 0x140000 1813 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 1814 copied to the credit register. Should be set and then reset after the 1815 configuration of the port has ended. */ 1816 #define PBF_REG_INIT_P0 0x140004 1817 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 1818 copied to the credit register. Should be set and then reset after the 1819 configuration of the port has ended. */ 1820 #define PBF_REG_INIT_P1 0x140008 1821 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 1822 copied to the credit register. Should be set and then reset after the 1823 configuration of the port has ended. */ 1824 #define PBF_REG_INIT_P4 0x14000c 1825 /* [RW 1] Enable for mac interface 0. */ 1826 #define PBF_REG_MAC_IF0_ENABLE 0x140030 1827 /* [RW 1] Enable for mac interface 1. */ 1828 #define PBF_REG_MAC_IF1_ENABLE 0x140034 1829 /* [RW 1] Enable for the loopback interface. */ 1830 #define PBF_REG_MAC_LB_ENABLE 0x140040 1831 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 1832 not suppoterd. */ 1833 #define PBF_REG_P0_ARB_THRSH 0x1400e4 1834 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 1835 #define PBF_REG_P0_CREDIT 0x140200 1836 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 1837 lines. */ 1838 #define PBF_REG_P0_INIT_CRD 0x1400d0 1839 /* [RW 1] Indication that pause is enabled for port 0. */ 1840 #define PBF_REG_P0_PAUSE_ENABLE 0x140014 1841 /* [R 8] Number of tasks in port 0 task queue. */ 1842 #define PBF_REG_P0_TASK_CNT 0x140204 1843 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */ 1844 #define PBF_REG_P1_CREDIT 0x140208 1845 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte 1846 lines. */ 1847 #define PBF_REG_P1_INIT_CRD 0x1400d4 1848 /* [R 8] Number of tasks in port 1 task queue. */ 1849 #define PBF_REG_P1_TASK_CNT 0x14020c 1850 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 1851 #define PBF_REG_P4_CREDIT 0x140210 1852 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 1853 lines. */ 1854 #define PBF_REG_P4_INIT_CRD 0x1400e0 1855 /* [R 8] Number of tasks in port 4 task queue. */ 1856 #define PBF_REG_P4_TASK_CNT 0x140214 1857 /* [RW 5] Interrupt mask register #0 read/write */ 1858 #define PBF_REG_PBF_INT_MASK 0x1401d4 1859 /* [R 5] Interrupt register #0 read */ 1860 #define PBF_REG_PBF_INT_STS 0x1401c8 1861 #define PB_REG_CONTROL 0 1862 /* [RW 2] Interrupt mask register #0 read/write */ 1863 #define PB_REG_PB_INT_MASK 0x28 1864 /* [R 2] Interrupt register #0 read */ 1865 #define PB_REG_PB_INT_STS 0x1c 1866 /* [RW 4] Parity mask register #0 read/write */ 1867 #define PB_REG_PB_PRTY_MASK 0x38 1868 /* [R 4] Parity register #0 read */ 1869 #define PB_REG_PB_PRTY_STS 0x2c 1870 #define PRS_REG_A_PRSU_20 0x40134 1871 /* [R 8] debug only: CFC load request current credit. Transaction based. */ 1872 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 1873 /* [R 8] debug only: CFC search request current credit. Transaction based. */ 1874 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 1875 /* [RW 6] The initial credit for the search message to the CFC interface. 1876 Credit is transaction based. */ 1877 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 1878 /* [RW 24] CID for port 0 if no match */ 1879 #define PRS_REG_CID_PORT_0 0x400fc 1880 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 1881 load response is reset and packet type is 0. Used in packet start message 1882 to TCM. */ 1883 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 1884 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 1885 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 1886 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 1887 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 1888 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC 1889 load response is set and packet type is 0. Used in packet start message 1890 to TCM. */ 1891 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 1892 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 1893 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 1894 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 1895 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 1896 /* [RW 32] The CM header for a match and packet type 1 for loopback port. 1897 Used in packet start message to TCM. */ 1898 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 1899 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 1900 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 1901 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 1902 /* [RW 32] The CM header for a match and packet type 0. Used in packet start 1903 message to TCM. */ 1904 #define PRS_REG_CM_HDR_TYPE_0 0x40078 1905 #define PRS_REG_CM_HDR_TYPE_1 0x4007c 1906 #define PRS_REG_CM_HDR_TYPE_2 0x40080 1907 #define PRS_REG_CM_HDR_TYPE_3 0x40084 1908 #define PRS_REG_CM_HDR_TYPE_4 0x40088 1909 /* [RW 32] The CM header in case there was not a match on the connection */ 1910 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8 1911 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 1912 #define PRS_REG_E1HOV_MODE 0x401c8 1913 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 1914 start message to TCM. */ 1915 #define PRS_REG_EVENT_ID_1 0x40054 1916 #define PRS_REG_EVENT_ID_2 0x40058 1917 #define PRS_REG_EVENT_ID_3 0x4005c 1918 /* [RW 16] The Ethernet type value for FCoE */ 1919 #define PRS_REG_FCOE_TYPE 0x401d0 1920 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC 1921 load request message. */ 1922 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 1923 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 1924 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 1925 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 1926 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 1927 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 1928 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 1929 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 1930 /* [RW 4] The increment value to send in the CFC load request message */ 1931 #define PRS_REG_INC_VALUE 0x40048 1932 /* [RW 1] If set indicates not to send messages to CFC on received packets */ 1933 #define PRS_REG_NIC_MODE 0x40138 1934 /* [RW 8] The 8-bit event ID for cases where there is no match on the 1935 connection. Used in packet start message to TCM. */ 1936 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070 1937 /* [ST 24] The number of input CFC flush packets */ 1938 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 1939 /* [ST 32] The number of cycles the Parser halted its operation since it 1940 could not allocate the next serial number */ 1941 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 1942 /* [ST 24] The number of input packets */ 1943 #define PRS_REG_NUM_OF_PACKETS 0x40124 1944 /* [ST 24] The number of input transparent flush packets */ 1945 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 1946 /* [RW 8] Context region for received Ethernet packet with a match and 1947 packet type 0. Used in CFC load request message */ 1948 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 1949 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 1950 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 1951 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 1952 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 1953 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 1954 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 1955 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 1956 /* [R 2] debug only: Number of pending requests for CAC on port 0. */ 1957 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 1958 /* [R 2] debug only: Number of pending requests for header parsing. */ 1959 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 1960 /* [R 1] Interrupt register #0 read */ 1961 #define PRS_REG_PRS_INT_STS 0x40188 1962 /* [RW 8] Parity mask register #0 read/write */ 1963 #define PRS_REG_PRS_PRTY_MASK 0x401a4 1964 /* [R 8] Parity register #0 read */ 1965 #define PRS_REG_PRS_PRTY_STS 0x40198 1966 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load 1967 request message */ 1968 #define PRS_REG_PURE_REGIONS 0x40024 1969 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 1970 serail number was released by SDM but cannot be used because a previous 1971 serial number was not released. */ 1972 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 1973 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 1974 serail number was released by SDM but cannot be used because a previous 1975 serial number was not released. */ 1976 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 1977 /* [R 4] debug only: SRC current credit. Transaction based. */ 1978 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 1979 /* [R 8] debug only: TCM current credit. Cycle based. */ 1980 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 1981 /* [R 8] debug only: TSDM current credit. Transaction based. */ 1982 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 1983 /* [R 6] Debug only: Number of used entries in the data FIFO */ 1984 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 1985 /* [R 7] Debug only: Number of used entries in the header FIFO */ 1986 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 1987 #define PXP2_REG_PGL_ADDR_88_F0 0x120534 1988 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 1989 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c 1990 #define PXP2_REG_PGL_ADDR_94_F0 0x120540 1991 #define PXP2_REG_PGL_CONTROL0 0x120490 1992 #define PXP2_REG_PGL_CONTROL1 0x120514 1993 /* [RW 32] third dword data of expansion rom request. this register is 1994 special. reading from it provides a vector outstanding read requests. if 1995 a bit is zero it means that a read request on the corresponding tag did 1996 not finish yet (not all completions have arrived for it) */ 1997 #define PXP2_REG_PGL_EXP_ROM2 0x120808 1998 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 1999 its[15:0]-address */ 2000 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 2001 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 2002 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 2003 #define PXP2_REG_PGL_INT_CSDM_3 0x120500 2004 #define PXP2_REG_PGL_INT_CSDM_4 0x120504 2005 #define PXP2_REG_PGL_INT_CSDM_5 0x120508 2006 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c 2007 #define PXP2_REG_PGL_INT_CSDM_7 0x120510 2008 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 2009 its[15:0]-address */ 2010 #define PXP2_REG_PGL_INT_TSDM_0 0x120494 2011 #define PXP2_REG_PGL_INT_TSDM_1 0x120498 2012 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c 2013 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 2014 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 2015 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 2016 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 2017 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 2018 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 2019 its[15:0]-address */ 2020 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4 2021 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8 2022 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc 2023 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0 2024 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4 2025 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8 2026 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc 2027 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0 2028 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 2029 its[15:0]-address */ 2030 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 2031 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 2032 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 2033 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 2034 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 2035 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 2036 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 2037 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 2038 /* [R 1] this bit indicates that a read request was blocked because of 2039 bus_master_en was deasserted */ 2040 #define PXP2_REG_PGL_READ_BLOCKED 0x120568 2041 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 2042 /* [R 18] debug only */ 2043 #define PXP2_REG_PGL_TXW_CDTS 0x12052c 2044 /* [R 1] this bit indicates that a write request was blocked because of 2045 bus_master_en was deasserted */ 2046 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 2047 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 2048 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 2049 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 2050 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 2051 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 2052 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 2053 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 2054 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 2055 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 2056 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 2057 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 2058 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 2059 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 2060 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 2061 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 2062 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 2063 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 2064 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 2065 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 2066 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 2067 #define PXP2_REG_PSWRQ_BW_L28 0x120318 2068 #define PXP2_REG_PSWRQ_BW_L28 0x120318 2069 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 2070 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 2071 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 2072 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc 2073 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 2074 #define PXP2_REG_PSWRQ_BW_RD 0x120324 2075 #define PXP2_REG_PSWRQ_BW_UB1 0x120238 2076 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 2077 #define PXP2_REG_PSWRQ_BW_UB11 0x120260 2078 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 2079 #define PXP2_REG_PSWRQ_BW_UB11 0x120260 2080 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c 2081 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 2082 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 2083 #define PXP2_REG_PSWRQ_BW_UB3 0x120240 2084 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c 2085 #define PXP2_REG_PSWRQ_BW_UB7 0x120250 2086 #define PXP2_REG_PSWRQ_BW_UB8 0x120254 2087 #define PXP2_REG_PSWRQ_BW_UB9 0x120258 2088 #define PXP2_REG_PSWRQ_BW_WR 0x120328 2089 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 2090 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 2091 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 2092 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 2093 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 2094 /* [RW 32] Interrupt mask register #0 read/write */ 2095 #define PXP2_REG_PXP2_INT_MASK_0 0x120578 2096 /* [R 32] Interrupt register #0 read */ 2097 #define PXP2_REG_PXP2_INT_STS_0 0x12056c 2098 #define PXP2_REG_PXP2_INT_STS_1 0x120608 2099 /* [RC 32] Interrupt register #0 read clear */ 2100 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 2101 /* [RW 32] Parity mask register #0 read/write */ 2102 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 2103 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 2104 /* [R 32] Parity register #0 read */ 2105 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 2106 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 2107 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives 2108 indication about backpressure) */ 2109 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 2110 /* [R 8] Debug only: The blocks counter - number of unused block ids */ 2111 #define PXP2_REG_RD_BLK_CNT 0x120418 2112 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 2113 Must be bigger than 6. Normally should not be changed. */ 2114 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 2115 /* [RW 2] CDU byte swapping mode configuration for master read requests */ 2116 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 2117 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 2118 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 2119 /* [R 1] PSWRD internal memories initialization is done */ 2120 #define PXP2_REG_RD_INIT_DONE 0x120370 2121 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2122 allocated for vq10 */ 2123 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 2124 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2125 allocated for vq11 */ 2126 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 2127 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2128 allocated for vq17 */ 2129 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 2130 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2131 allocated for vq18 */ 2132 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 2133 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2134 allocated for vq19 */ 2135 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 2136 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2137 allocated for vq22 */ 2138 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 2139 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2140 allocated for vq6 */ 2141 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 2142 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be 2143 allocated for vq9 */ 2144 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 2145 /* [RW 2] PBF byte swapping mode configuration for master read requests */ 2146 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 2147 /* [R 1] Debug only: Indication if delivery ports are idle */ 2148 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 2149 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 2150 /* [RW 2] QM byte swapping mode configuration for master read requests */ 2151 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 2152 /* [R 7] Debug only: The SR counter - number of unused sub request ids */ 2153 #define PXP2_REG_RD_SR_CNT 0x120414 2154 /* [RW 2] SRC byte swapping mode configuration for master read requests */ 2155 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 2156 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 2157 be bigger than 1. Normally should not be changed. */ 2158 #define PXP2_REG_RD_SR_NUM_CFG 0x120408 2159 /* [RW 1] Signals the PSWRD block to start initializing internal memories */ 2160 #define PXP2_REG_RD_START_INIT 0x12036c 2161 /* [RW 2] TM byte swapping mode configuration for master read requests */ 2162 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 2163 /* [RW 10] Bandwidth addition to VQ0 write requests */ 2164 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 2165 /* [RW 10] Bandwidth addition to VQ12 read requests */ 2166 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 2167 /* [RW 10] Bandwidth addition to VQ13 read requests */ 2168 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 2169 /* [RW 10] Bandwidth addition to VQ14 read requests */ 2170 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 2171 /* [RW 10] Bandwidth addition to VQ15 read requests */ 2172 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 2173 /* [RW 10] Bandwidth addition to VQ16 read requests */ 2174 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 2175 /* [RW 10] Bandwidth addition to VQ17 read requests */ 2176 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 2177 /* [RW 10] Bandwidth addition to VQ18 read requests */ 2178 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 2179 /* [RW 10] Bandwidth addition to VQ19 read requests */ 2180 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 2181 /* [RW 10] Bandwidth addition to VQ20 read requests */ 2182 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 2183 /* [RW 10] Bandwidth addition to VQ22 read requests */ 2184 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 2185 /* [RW 10] Bandwidth addition to VQ23 read requests */ 2186 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 2187 /* [RW 10] Bandwidth addition to VQ24 read requests */ 2188 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 2189 /* [RW 10] Bandwidth addition to VQ25 read requests */ 2190 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 2191 /* [RW 10] Bandwidth addition to VQ26 read requests */ 2192 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 2193 /* [RW 10] Bandwidth addition to VQ27 read requests */ 2194 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 2195 /* [RW 10] Bandwidth addition to VQ4 read requests */ 2196 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 2197 /* [RW 10] Bandwidth addition to VQ5 read requests */ 2198 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 2199 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 2200 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac 2201 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 2202 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc 2203 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 2204 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 2205 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 2206 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 2207 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 2208 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 2209 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 2210 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec 2211 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 2212 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 2213 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 2214 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 2215 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 2216 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 2217 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 2218 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc 2219 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 2220 #define PXP2_REG_RQ_BW_RD_L22 0x120300 2221 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 2222 #define PXP2_REG_RQ_BW_RD_L23 0x120304 2223 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 2224 #define PXP2_REG_RQ_BW_RD_L24 0x120308 2225 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 2226 #define PXP2_REG_RQ_BW_RD_L25 0x12030c 2227 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 2228 #define PXP2_REG_RQ_BW_RD_L26 0x120310 2229 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 2230 #define PXP2_REG_RQ_BW_RD_L27 0x120314 2231 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 2232 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc 2233 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 2234 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 2235 /* [RW 7] Bandwidth upper bound for VQ0 read requests */ 2236 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 2237 /* [RW 7] Bandwidth upper bound for VQ12 read requests */ 2238 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 2239 /* [RW 7] Bandwidth upper bound for VQ13 read requests */ 2240 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 2241 /* [RW 7] Bandwidth upper bound for VQ14 read requests */ 2242 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 2243 /* [RW 7] Bandwidth upper bound for VQ15 read requests */ 2244 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 2245 /* [RW 7] Bandwidth upper bound for VQ16 read requests */ 2246 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 2247 /* [RW 7] Bandwidth upper bound for VQ17 read requests */ 2248 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 2249 /* [RW 7] Bandwidth upper bound for VQ18 read requests */ 2250 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 2251 /* [RW 7] Bandwidth upper bound for VQ19 read requests */ 2252 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 2253 /* [RW 7] Bandwidth upper bound for VQ20 read requests */ 2254 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 2255 /* [RW 7] Bandwidth upper bound for VQ22 read requests */ 2256 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 2257 /* [RW 7] Bandwidth upper bound for VQ23 read requests */ 2258 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 2259 /* [RW 7] Bandwidth upper bound for VQ24 read requests */ 2260 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 2261 /* [RW 7] Bandwidth upper bound for VQ25 read requests */ 2262 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 2263 /* [RW 7] Bandwidth upper bound for VQ26 read requests */ 2264 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 2265 /* [RW 7] Bandwidth upper bound for VQ27 read requests */ 2266 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 2267 /* [RW 7] Bandwidth upper bound for VQ4 read requests */ 2268 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 2269 /* [RW 7] Bandwidth upper bound for VQ5 read requests */ 2270 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 2271 /* [RW 10] Bandwidth addition to VQ29 write requests */ 2272 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 2273 /* [RW 10] Bandwidth addition to VQ30 write requests */ 2274 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 2275 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 2276 #define PXP2_REG_RQ_BW_WR_L29 0x12031c 2277 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 2278 #define PXP2_REG_RQ_BW_WR_L30 0x120320 2279 /* [RW 7] Bandwidth upper bound for VQ29 */ 2280 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 2281 /* [RW 7] Bandwidth upper bound for VQ30 */ 2282 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 2283 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 2284 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 2285 /* [RW 2] Endian mode for cdu */ 2286 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 2287 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 2288 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 2289 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 2290 -128k */ 2291 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 2292 /* [R 1] 1' indicates that the requester has finished its internal 2293 configuration */ 2294 #define PXP2_REG_RQ_CFG_DONE 0x1201b4 2295 /* [RW 2] Endian mode for debug */ 2296 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 2297 /* [RW 1] When '1'; requests will enter input buffers but wont get out 2298 towards the glue */ 2299 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 2300 /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */ 2301 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 2302 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 2303 be asserted */ 2304 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c 2305 /* [RW 2] Endian mode for hc */ 2306 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 2307 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 2308 compatibility needs; Note that different registers are used per mode */ 2309 #define PXP2_REG_RQ_ILT_MODE 0x1205b4 2310 /* [WB 53] Onchip address table */ 2311 #define PXP2_REG_RQ_ONCHIP_AT 0x122000 2312 /* [WB 53] Onchip address table - B0 */ 2313 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 2314 /* [RW 13] Pending read limiter threshold; in Dwords */ 2315 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c 2316 /* [RW 2] Endian mode for qm */ 2317 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 2318 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 2319 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 2320 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 2321 -128k */ 2322 #define PXP2_REG_RQ_QM_P_SIZE 0x120050 2323 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 2324 #define PXP2_REG_RQ_RBC_DONE 0x1201b0 2325 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 2326 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 2327 #define PXP2_REG_RQ_RD_MBS0 0x120160 2328 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 2329 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 2330 #define PXP2_REG_RQ_RD_MBS1 0x120168 2331 /* [RW 2] Endian mode for src */ 2332 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 2333 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 2334 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 2335 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 2336 -128k */ 2337 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 2338 /* [RW 2] Endian mode for tm */ 2339 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 2340 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 2341 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 2342 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 2343 -128k */ 2344 #define PXP2_REG_RQ_TM_P_SIZE 0x120034 2345 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 2346 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 2347 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 2348 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 2349 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 2350 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 2351 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 2352 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 2353 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 2354 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 2355 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 2356 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 2357 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 2358 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 2359 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 2360 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 2361 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 2362 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 2363 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 2364 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 2365 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 2366 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 2367 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 2368 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 2369 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 2370 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 2371 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 2372 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 2373 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 2374 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 2375 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 2376 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 2377 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 2378 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 2379 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 2380 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 2381 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 2382 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 2383 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 2384 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 2385 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 2386 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 2387 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 2388 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 2389 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 2390 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 2391 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 2392 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 2393 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 2394 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 2395 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 2396 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 2397 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 2398 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 2399 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 2400 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 2401 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 2402 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 2403 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 2404 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 2405 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 2406 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 2407 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 2408 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 2409 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 2410 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 2411 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 2412 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 2413 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 2414 001:256B; 010: 512B; */ 2415 #define PXP2_REG_RQ_WR_MBS0 0x12015c 2416 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 2417 001:256B; 010: 512B; */ 2418 #define PXP2_REG_RQ_WR_MBS1 0x120164 2419 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2420 buffer reaches this number has_payload will be asserted */ 2421 #define PXP2_REG_WR_CDU_MPS 0x1205f0 2422 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2423 buffer reaches this number has_payload will be asserted */ 2424 #define PXP2_REG_WR_CSDM_MPS 0x1205d0 2425 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2426 buffer reaches this number has_payload will be asserted */ 2427 #define PXP2_REG_WR_DBG_MPS 0x1205e8 2428 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2429 buffer reaches this number has_payload will be asserted */ 2430 #define PXP2_REG_WR_DMAE_MPS 0x1205ec 2431 /* [RW 10] if Number of entries in dmae fifo will be higher than this 2432 threshold then has_payload indication will be asserted; the default value 2433 should be equal to > write MBS size! */ 2434 #define PXP2_REG_WR_DMAE_TH 0x120368 2435 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2436 buffer reaches this number has_payload will be asserted */ 2437 #define PXP2_REG_WR_HC_MPS 0x1205c8 2438 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2439 buffer reaches this number has_payload will be asserted */ 2440 #define PXP2_REG_WR_QM_MPS 0x1205dc 2441 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 2442 #define PXP2_REG_WR_REV_MODE 0x120670 2443 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2444 buffer reaches this number has_payload will be asserted */ 2445 #define PXP2_REG_WR_SRC_MPS 0x1205e4 2446 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2447 buffer reaches this number has_payload will be asserted */ 2448 #define PXP2_REG_WR_TM_MPS 0x1205e0 2449 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2450 buffer reaches this number has_payload will be asserted */ 2451 #define PXP2_REG_WR_TSDM_MPS 0x1205d4 2452 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this 2453 threshold then has_payload indication will be asserted; the default value 2454 should be equal to > write MBS size! */ 2455 #define PXP2_REG_WR_USDMDP_TH 0x120348 2456 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2457 buffer reaches this number has_payload will be asserted */ 2458 #define PXP2_REG_WR_USDM_MPS 0x1205cc 2459 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 2460 buffer reaches this number has_payload will be asserted */ 2461 #define PXP2_REG_WR_XSDM_MPS 0x1205d8 2462 /* [R 1] debug only: Indication if PSWHST arbiter is idle */ 2463 #define PXP_REG_HST_ARB_IS_IDLE 0x103004 2464 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 2465 this client is waiting for the arbiter. */ 2466 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 2467 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 2468 should update accoring to 'hst_discard_doorbells' register when the state 2469 machine is idle */ 2470 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 2471 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 2472 means this PSWHST is discarding inputs from this client. Each bit should 2473 update accoring to 'hst_discard_internal_writes' register when the state 2474 machine is idle. */ 2475 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 2476 /* [WB 160] Used for initialization of the inbound interrupts memory */ 2477 #define PXP_REG_HST_INBOUND_INT 0x103800 2478 /* [RW 32] Interrupt mask register #0 read/write */ 2479 #define PXP_REG_PXP_INT_MASK_0 0x103074 2480 #define PXP_REG_PXP_INT_MASK_1 0x103084 2481 /* [R 32] Interrupt register #0 read */ 2482 #define PXP_REG_PXP_INT_STS_0 0x103068 2483 #define PXP_REG_PXP_INT_STS_1 0x103078 2484 /* [RC 32] Interrupt register #0 read clear */ 2485 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 2486 /* [RW 26] Parity mask register #0 read/write */ 2487 #define PXP_REG_PXP_PRTY_MASK 0x103094 2488 /* [R 26] Parity register #0 read */ 2489 #define PXP_REG_PXP_PRTY_STS 0x103088 2490 /* [RW 4] The activity counter initial increment value sent in the load 2491 request */ 2492 #define QM_REG_ACTCTRINITVAL_0 0x168040 2493 #define QM_REG_ACTCTRINITVAL_1 0x168044 2494 #define QM_REG_ACTCTRINITVAL_2 0x168048 2495 #define QM_REG_ACTCTRINITVAL_3 0x16804c 2496 /* [RW 32] The base logical address (in bytes) of each physical queue. The 2497 index I represents the physical queue number. The 12 lsbs are ignore and 2498 considered zero so practically there are only 20 bits in this register; 2499 queues 63-0 */ 2500 #define QM_REG_BASEADDR 0x168900 2501 /* [RW 16] The byte credit cost for each task. This value is for both ports */ 2502 #define QM_REG_BYTECRDCOST 0x168234 2503 /* [RW 16] The initial byte credit value for both ports. */ 2504 #define QM_REG_BYTECRDINITVAL 0x168238 2505 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2506 queue uses port 0 else it uses port 1; queues 31-0 */ 2507 #define QM_REG_BYTECRDPORT_LSB 0x168228 2508 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2509 queue uses port 0 else it uses port 1; queues 95-64 */ 2510 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 2511 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2512 queue uses port 0 else it uses port 1; queues 63-32 */ 2513 #define QM_REG_BYTECRDPORT_MSB 0x168224 2514 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2515 queue uses port 0 else it uses port 1; queues 127-96 */ 2516 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 2517 /* [RW 16] The byte credit value that if above the QM is considered almost 2518 full */ 2519 #define QM_REG_BYTECREDITAFULLTHR 0x168094 2520 /* [RW 4] The initial credit for interface */ 2521 #define QM_REG_CMINITCRD_0 0x1680cc 2522 #define QM_REG_CMINITCRD_1 0x1680d0 2523 #define QM_REG_CMINITCRD_2 0x1680d4 2524 #define QM_REG_CMINITCRD_3 0x1680d8 2525 #define QM_REG_CMINITCRD_4 0x1680dc 2526 #define QM_REG_CMINITCRD_5 0x1680e0 2527 #define QM_REG_CMINITCRD_6 0x1680e4 2528 #define QM_REG_CMINITCRD_7 0x1680e8 2529 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 2530 is masked */ 2531 #define QM_REG_CMINTEN 0x1680ec 2532 /* [RW 12] A bit vector which indicates which one of the queues are tied to 2533 interface 0 */ 2534 #define QM_REG_CMINTVOQMASK_0 0x1681f4 2535 #define QM_REG_CMINTVOQMASK_1 0x1681f8 2536 #define QM_REG_CMINTVOQMASK_2 0x1681fc 2537 #define QM_REG_CMINTVOQMASK_3 0x168200 2538 #define QM_REG_CMINTVOQMASK_4 0x168204 2539 #define QM_REG_CMINTVOQMASK_5 0x168208 2540 #define QM_REG_CMINTVOQMASK_6 0x16820c 2541 #define QM_REG_CMINTVOQMASK_7 0x168210 2542 /* [RW 20] The number of connections divided by 16 which dictates the size 2543 of each queue which belongs to even function number. */ 2544 #define QM_REG_CONNNUM_0 0x168020 2545 /* [R 6] Keep the fill level of the fifo from write client 4 */ 2546 #define QM_REG_CQM_WRC_FIFOLVL 0x168018 2547 /* [RW 8] The context regions sent in the CFC load request */ 2548 #define QM_REG_CTXREG_0 0x168030 2549 #define QM_REG_CTXREG_1 0x168034 2550 #define QM_REG_CTXREG_2 0x168038 2551 #define QM_REG_CTXREG_3 0x16803c 2552 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 2553 bypass enable */ 2554 #define QM_REG_ENBYPVOQMASK 0x16823c 2555 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 2556 physical queue uses the byte credit; queues 31-0 */ 2557 #define QM_REG_ENBYTECRD_LSB 0x168220 2558 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 2559 physical queue uses the byte credit; queues 95-64 */ 2560 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 2561 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 2562 physical queue uses the byte credit; queues 63-32 */ 2563 #define QM_REG_ENBYTECRD_MSB 0x16821c 2564 /* [RW 32] A bit mask per each physical queue. If a bit is set then the 2565 physical queue uses the byte credit; queues 127-96 */ 2566 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 2567 /* [RW 4] If cleared then the secondary interface will not be served by the 2568 RR arbiter */ 2569 #define QM_REG_ENSEC 0x1680f0 2570 /* [RW 32] NA */ 2571 #define QM_REG_FUNCNUMSEL_LSB 0x168230 2572 /* [RW 32] NA */ 2573 #define QM_REG_FUNCNUMSEL_MSB 0x16822c 2574 /* [RW 32] A mask register to mask the Almost empty signals which will not 2575 be use for the almost empty indication to the HW block; queues 31:0 */ 2576 #define QM_REG_HWAEMPTYMASK_LSB 0x168218 2577 /* [RW 32] A mask register to mask the Almost empty signals which will not 2578 be use for the almost empty indication to the HW block; queues 95-64 */ 2579 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 2580 /* [RW 32] A mask register to mask the Almost empty signals which will not 2581 be use for the almost empty indication to the HW block; queues 63:32 */ 2582 #define QM_REG_HWAEMPTYMASK_MSB 0x168214 2583 /* [RW 32] A mask register to mask the Almost empty signals which will not 2584 be use for the almost empty indication to the HW block; queues 127-96 */ 2585 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 2586 /* [RW 4] The number of outstanding request to CFC */ 2587 #define QM_REG_OUTLDREQ 0x168804 2588 /* [RC 1] A flag to indicate that overflow error occurred in one of the 2589 queues. */ 2590 #define QM_REG_OVFERROR 0x16805c 2591 /* [RC 7] the Q were the qverflow occurs */ 2592 #define QM_REG_OVFQNUM 0x168058 2593 /* [R 16] Pause state for physical queues 15-0 */ 2594 #define QM_REG_PAUSESTATE0 0x168410 2595 /* [R 16] Pause state for physical queues 31-16 */ 2596 #define QM_REG_PAUSESTATE1 0x168414 2597 /* [R 16] Pause state for physical queues 47-32 */ 2598 #define QM_REG_PAUSESTATE2 0x16e684 2599 /* [R 16] Pause state for physical queues 63-48 */ 2600 #define QM_REG_PAUSESTATE3 0x16e688 2601 /* [R 16] Pause state for physical queues 79-64 */ 2602 #define QM_REG_PAUSESTATE4 0x16e68c 2603 /* [R 16] Pause state for physical queues 95-80 */ 2604 #define QM_REG_PAUSESTATE5 0x16e690 2605 /* [R 16] Pause state for physical queues 111-96 */ 2606 #define QM_REG_PAUSESTATE6 0x16e694 2607 /* [R 16] Pause state for physical queues 127-112 */ 2608 #define QM_REG_PAUSESTATE7 0x16e698 2609 /* [RW 2] The PCI attributes field used in the PCI request. */ 2610 #define QM_REG_PCIREQAT 0x168054 2611 /* [R 16] The byte credit of port 0 */ 2612 #define QM_REG_PORT0BYTECRD 0x168300 2613 /* [R 16] The byte credit of port 1 */ 2614 #define QM_REG_PORT1BYTECRD 0x168304 2615 /* [RW 3] pci function number of queues 15-0 */ 2616 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc 2617 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0 2618 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4 2619 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8 2620 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc 2621 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0 2622 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4 2623 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8 2624 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 2625 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 2626 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 2627 #define QM_REG_PTRTBL 0x168a00 2628 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 2629 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 2630 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 2631 #define QM_REG_PTRTBL_EXT_A 0x16e200 2632 /* [RW 2] Interrupt mask register #0 read/write */ 2633 #define QM_REG_QM_INT_MASK 0x168444 2634 /* [R 2] Interrupt register #0 read */ 2635 #define QM_REG_QM_INT_STS 0x168438 2636 /* [RW 12] Parity mask register #0 read/write */ 2637 #define QM_REG_QM_PRTY_MASK 0x168454 2638 /* [R 12] Parity register #0 read */ 2639 #define QM_REG_QM_PRTY_STS 0x168448 2640 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 2641 #define QM_REG_QSTATUS_HIGH 0x16802c 2642 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 2643 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 2644 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 2645 #define QM_REG_QSTATUS_LOW 0x168028 2646 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 2647 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 2648 /* [R 24] The number of tasks queued for each queue; queues 63-0 */ 2649 #define QM_REG_QTASKCTR_0 0x168308 2650 /* [R 24] The number of tasks queued for each queue; queues 127-64 */ 2651 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 2652 /* [RW 4] Queue tied to VOQ */ 2653 #define QM_REG_QVOQIDX_0 0x1680f4 2654 #define QM_REG_QVOQIDX_10 0x16811c 2655 #define QM_REG_QVOQIDX_100 0x16e49c 2656 #define QM_REG_QVOQIDX_101 0x16e4a0 2657 #define QM_REG_QVOQIDX_102 0x16e4a4 2658 #define QM_REG_QVOQIDX_103 0x16e4a8 2659 #define QM_REG_QVOQIDX_104 0x16e4ac 2660 #define QM_REG_QVOQIDX_105 0x16e4b0 2661 #define QM_REG_QVOQIDX_106 0x16e4b4 2662 #define QM_REG_QVOQIDX_107 0x16e4b8 2663 #define QM_REG_QVOQIDX_108 0x16e4bc 2664 #define QM_REG_QVOQIDX_109 0x16e4c0 2665 #define QM_REG_QVOQIDX_100 0x16e49c 2666 #define QM_REG_QVOQIDX_101 0x16e4a0 2667 #define QM_REG_QVOQIDX_102 0x16e4a4 2668 #define QM_REG_QVOQIDX_103 0x16e4a8 2669 #define QM_REG_QVOQIDX_104 0x16e4ac 2670 #define QM_REG_QVOQIDX_105 0x16e4b0 2671 #define QM_REG_QVOQIDX_106 0x16e4b4 2672 #define QM_REG_QVOQIDX_107 0x16e4b8 2673 #define QM_REG_QVOQIDX_108 0x16e4bc 2674 #define QM_REG_QVOQIDX_109 0x16e4c0 2675 #define QM_REG_QVOQIDX_11 0x168120 2676 #define QM_REG_QVOQIDX_110 0x16e4c4 2677 #define QM_REG_QVOQIDX_111 0x16e4c8 2678 #define QM_REG_QVOQIDX_112 0x16e4cc 2679 #define QM_REG_QVOQIDX_113 0x16e4d0 2680 #define QM_REG_QVOQIDX_114 0x16e4d4 2681 #define QM_REG_QVOQIDX_115 0x16e4d8 2682 #define QM_REG_QVOQIDX_116 0x16e4dc 2683 #define QM_REG_QVOQIDX_117 0x16e4e0 2684 #define QM_REG_QVOQIDX_118 0x16e4e4 2685 #define QM_REG_QVOQIDX_119 0x16e4e8 2686 #define QM_REG_QVOQIDX_110 0x16e4c4 2687 #define QM_REG_QVOQIDX_111 0x16e4c8 2688 #define QM_REG_QVOQIDX_112 0x16e4cc 2689 #define QM_REG_QVOQIDX_113 0x16e4d0 2690 #define QM_REG_QVOQIDX_114 0x16e4d4 2691 #define QM_REG_QVOQIDX_115 0x16e4d8 2692 #define QM_REG_QVOQIDX_116 0x16e4dc 2693 #define QM_REG_QVOQIDX_117 0x16e4e0 2694 #define QM_REG_QVOQIDX_118 0x16e4e4 2695 #define QM_REG_QVOQIDX_119 0x16e4e8 2696 #define QM_REG_QVOQIDX_12 0x168124 2697 #define QM_REG_QVOQIDX_120 0x16e4ec 2698 #define QM_REG_QVOQIDX_121 0x16e4f0 2699 #define QM_REG_QVOQIDX_122 0x16e4f4 2700 #define QM_REG_QVOQIDX_123 0x16e4f8 2701 #define QM_REG_QVOQIDX_124 0x16e4fc 2702 #define QM_REG_QVOQIDX_125 0x16e500 2703 #define QM_REG_QVOQIDX_126 0x16e504 2704 #define QM_REG_QVOQIDX_127 0x16e508 2705 #define QM_REG_QVOQIDX_120 0x16e4ec 2706 #define QM_REG_QVOQIDX_121 0x16e4f0 2707 #define QM_REG_QVOQIDX_122 0x16e4f4 2708 #define QM_REG_QVOQIDX_123 0x16e4f8 2709 #define QM_REG_QVOQIDX_124 0x16e4fc 2710 #define QM_REG_QVOQIDX_125 0x16e500 2711 #define QM_REG_QVOQIDX_126 0x16e504 2712 #define QM_REG_QVOQIDX_127 0x16e508 2713 #define QM_REG_QVOQIDX_13 0x168128 2714 #define QM_REG_QVOQIDX_14 0x16812c 2715 #define QM_REG_QVOQIDX_15 0x168130 2716 #define QM_REG_QVOQIDX_16 0x168134 2717 #define QM_REG_QVOQIDX_17 0x168138 2718 #define QM_REG_QVOQIDX_21 0x168148 2719 #define QM_REG_QVOQIDX_22 0x16814c 2720 #define QM_REG_QVOQIDX_23 0x168150 2721 #define QM_REG_QVOQIDX_24 0x168154 2722 #define QM_REG_QVOQIDX_25 0x168158 2723 #define QM_REG_QVOQIDX_26 0x16815c 2724 #define QM_REG_QVOQIDX_27 0x168160 2725 #define QM_REG_QVOQIDX_28 0x168164 2726 #define QM_REG_QVOQIDX_29 0x168168 2727 #define QM_REG_QVOQIDX_30 0x16816c 2728 #define QM_REG_QVOQIDX_31 0x168170 2729 #define QM_REG_QVOQIDX_32 0x168174 2730 #define QM_REG_QVOQIDX_33 0x168178 2731 #define QM_REG_QVOQIDX_34 0x16817c 2732 #define QM_REG_QVOQIDX_35 0x168180 2733 #define QM_REG_QVOQIDX_36 0x168184 2734 #define QM_REG_QVOQIDX_37 0x168188 2735 #define QM_REG_QVOQIDX_38 0x16818c 2736 #define QM_REG_QVOQIDX_39 0x168190 2737 #define QM_REG_QVOQIDX_40 0x168194 2738 #define QM_REG_QVOQIDX_41 0x168198 2739 #define QM_REG_QVOQIDX_42 0x16819c 2740 #define QM_REG_QVOQIDX_43 0x1681a0 2741 #define QM_REG_QVOQIDX_44 0x1681a4 2742 #define QM_REG_QVOQIDX_45 0x1681a8 2743 #define QM_REG_QVOQIDX_46 0x1681ac 2744 #define QM_REG_QVOQIDX_47 0x1681b0 2745 #define QM_REG_QVOQIDX_48 0x1681b4 2746 #define QM_REG_QVOQIDX_49 0x1681b8 2747 #define QM_REG_QVOQIDX_5 0x168108 2748 #define QM_REG_QVOQIDX_50 0x1681bc 2749 #define QM_REG_QVOQIDX_51 0x1681c0 2750 #define QM_REG_QVOQIDX_52 0x1681c4 2751 #define QM_REG_QVOQIDX_53 0x1681c8 2752 #define QM_REG_QVOQIDX_54 0x1681cc 2753 #define QM_REG_QVOQIDX_55 0x1681d0 2754 #define QM_REG_QVOQIDX_56 0x1681d4 2755 #define QM_REG_QVOQIDX_57 0x1681d8 2756 #define QM_REG_QVOQIDX_58 0x1681dc 2757 #define QM_REG_QVOQIDX_59 0x1681e0 2758 #define QM_REG_QVOQIDX_50 0x1681bc 2759 #define QM_REG_QVOQIDX_51 0x1681c0 2760 #define QM_REG_QVOQIDX_52 0x1681c4 2761 #define QM_REG_QVOQIDX_53 0x1681c8 2762 #define QM_REG_QVOQIDX_54 0x1681cc 2763 #define QM_REG_QVOQIDX_55 0x1681d0 2764 #define QM_REG_QVOQIDX_56 0x1681d4 2765 #define QM_REG_QVOQIDX_57 0x1681d8 2766 #define QM_REG_QVOQIDX_58 0x1681dc 2767 #define QM_REG_QVOQIDX_59 0x1681e0 2768 #define QM_REG_QVOQIDX_6 0x16810c 2769 #define QM_REG_QVOQIDX_60 0x1681e4 2770 #define QM_REG_QVOQIDX_61 0x1681e8 2771 #define QM_REG_QVOQIDX_62 0x1681ec 2772 #define QM_REG_QVOQIDX_63 0x1681f0 2773 #define QM_REG_QVOQIDX_64 0x16e40c 2774 #define QM_REG_QVOQIDX_65 0x16e410 2775 #define QM_REG_QVOQIDX_66 0x16e414 2776 #define QM_REG_QVOQIDX_67 0x16e418 2777 #define QM_REG_QVOQIDX_68 0x16e41c 2778 #define QM_REG_QVOQIDX_69 0x16e420 2779 #define QM_REG_QVOQIDX_60 0x1681e4 2780 #define QM_REG_QVOQIDX_61 0x1681e8 2781 #define QM_REG_QVOQIDX_62 0x1681ec 2782 #define QM_REG_QVOQIDX_63 0x1681f0 2783 #define QM_REG_QVOQIDX_64 0x16e40c 2784 #define QM_REG_QVOQIDX_65 0x16e410 2785 #define QM_REG_QVOQIDX_69 0x16e420 2786 #define QM_REG_QVOQIDX_7 0x168110 2787 #define QM_REG_QVOQIDX_70 0x16e424 2788 #define QM_REG_QVOQIDX_71 0x16e428 2789 #define QM_REG_QVOQIDX_72 0x16e42c 2790 #define QM_REG_QVOQIDX_73 0x16e430 2791 #define QM_REG_QVOQIDX_74 0x16e434 2792 #define QM_REG_QVOQIDX_75 0x16e438 2793 #define QM_REG_QVOQIDX_76 0x16e43c 2794 #define QM_REG_QVOQIDX_77 0x16e440 2795 #define QM_REG_QVOQIDX_78 0x16e444 2796 #define QM_REG_QVOQIDX_79 0x16e448 2797 #define QM_REG_QVOQIDX_70 0x16e424 2798 #define QM_REG_QVOQIDX_71 0x16e428 2799 #define QM_REG_QVOQIDX_72 0x16e42c 2800 #define QM_REG_QVOQIDX_73 0x16e430 2801 #define QM_REG_QVOQIDX_74 0x16e434 2802 #define QM_REG_QVOQIDX_75 0x16e438 2803 #define QM_REG_QVOQIDX_76 0x16e43c 2804 #define QM_REG_QVOQIDX_77 0x16e440 2805 #define QM_REG_QVOQIDX_78 0x16e444 2806 #define QM_REG_QVOQIDX_79 0x16e448 2807 #define QM_REG_QVOQIDX_8 0x168114 2808 #define QM_REG_QVOQIDX_80 0x16e44c 2809 #define QM_REG_QVOQIDX_81 0x16e450 2810 #define QM_REG_QVOQIDX_82 0x16e454 2811 #define QM_REG_QVOQIDX_83 0x16e458 2812 #define QM_REG_QVOQIDX_84 0x16e45c 2813 #define QM_REG_QVOQIDX_85 0x16e460 2814 #define QM_REG_QVOQIDX_86 0x16e464 2815 #define QM_REG_QVOQIDX_87 0x16e468 2816 #define QM_REG_QVOQIDX_88 0x16e46c 2817 #define QM_REG_QVOQIDX_89 0x16e470 2818 #define QM_REG_QVOQIDX_80 0x16e44c 2819 #define QM_REG_QVOQIDX_81 0x16e450 2820 #define QM_REG_QVOQIDX_85 0x16e460 2821 #define QM_REG_QVOQIDX_86 0x16e464 2822 #define QM_REG_QVOQIDX_87 0x16e468 2823 #define QM_REG_QVOQIDX_88 0x16e46c 2824 #define QM_REG_QVOQIDX_89 0x16e470 2825 #define QM_REG_QVOQIDX_9 0x168118 2826 #define QM_REG_QVOQIDX_90 0x16e474 2827 #define QM_REG_QVOQIDX_91 0x16e478 2828 #define QM_REG_QVOQIDX_92 0x16e47c 2829 #define QM_REG_QVOQIDX_93 0x16e480 2830 #define QM_REG_QVOQIDX_94 0x16e484 2831 #define QM_REG_QVOQIDX_95 0x16e488 2832 #define QM_REG_QVOQIDX_96 0x16e48c 2833 #define QM_REG_QVOQIDX_97 0x16e490 2834 #define QM_REG_QVOQIDX_98 0x16e494 2835 #define QM_REG_QVOQIDX_99 0x16e498 2836 #define QM_REG_QVOQIDX_90 0x16e474 2837 #define QM_REG_QVOQIDX_91 0x16e478 2838 #define QM_REG_QVOQIDX_92 0x16e47c 2839 #define QM_REG_QVOQIDX_93 0x16e480 2840 #define QM_REG_QVOQIDX_94 0x16e484 2841 #define QM_REG_QVOQIDX_95 0x16e488 2842 #define QM_REG_QVOQIDX_96 0x16e48c 2843 #define QM_REG_QVOQIDX_97 0x16e490 2844 #define QM_REG_QVOQIDX_98 0x16e494 2845 #define QM_REG_QVOQIDX_99 0x16e498 2846 /* [RW 1] Initialization bit command */ 2847 #define QM_REG_SOFT_RESET 0x168428 2848 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 2849 #define QM_REG_TASKCRDCOST_0 0x16809c 2850 #define QM_REG_TASKCRDCOST_1 0x1680a0 2851 #define QM_REG_TASKCRDCOST_10 0x1680c4 2852 #define QM_REG_TASKCRDCOST_11 0x1680c8 2853 #define QM_REG_TASKCRDCOST_2 0x1680a4 2854 #define QM_REG_TASKCRDCOST_4 0x1680ac 2855 #define QM_REG_TASKCRDCOST_5 0x1680b0 2856 /* [R 6] Keep the fill level of the fifo from write client 3 */ 2857 #define QM_REG_TQM_WRC_FIFOLVL 0x168010 2858 /* [R 6] Keep the fill level of the fifo from write client 2 */ 2859 #define QM_REG_UQM_WRC_FIFOLVL 0x168008 2860 /* [RC 32] Credit update error register */ 2861 #define QM_REG_VOQCRDERRREG 0x168408 2862 /* [R 16] The credit value for each VOQ */ 2863 #define QM_REG_VOQCREDIT_0 0x1682d0 2864 #define QM_REG_VOQCREDIT_1 0x1682d4 2865 #define QM_REG_VOQCREDIT_10 0x1682f8 2866 #define QM_REG_VOQCREDIT_11 0x1682fc 2867 #define QM_REG_VOQCREDIT_4 0x1682e0 2868 /* [RW 16] The credit value that if above the QM is considered almost full */ 2869 #define QM_REG_VOQCREDITAFULLTHR 0x168090 2870 /* [RW 16] The init and maximum credit for each VoQ */ 2871 #define QM_REG_VOQINITCREDIT_0 0x168060 2872 #define QM_REG_VOQINITCREDIT_1 0x168064 2873 #define QM_REG_VOQINITCREDIT_10 0x168088 2874 #define QM_REG_VOQINITCREDIT_11 0x16808c 2875 #define QM_REG_VOQINITCREDIT_2 0x168068 2876 #define QM_REG_VOQINITCREDIT_4 0x168070 2877 #define QM_REG_VOQINITCREDIT_5 0x168074 2878 /* [RW 1] The port of which VOQ belongs */ 2879 #define QM_REG_VOQPORT_0 0x1682a0 2880 #define QM_REG_VOQPORT_1 0x1682a4 2881 #define QM_REG_VOQPORT_10 0x1682c8 2882 #define QM_REG_VOQPORT_11 0x1682cc 2883 #define QM_REG_VOQPORT_2 0x1682a8 2884 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2885 #define QM_REG_VOQQMASK_0_LSB 0x168240 2886 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2887 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 2888 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2889 #define QM_REG_VOQQMASK_0_MSB 0x168244 2890 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2891 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 2892 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2893 #define QM_REG_VOQQMASK_10_LSB 0x168290 2894 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2895 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 2896 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2897 #define QM_REG_VOQQMASK_10_MSB 0x168294 2898 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2899 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 2900 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2901 #define QM_REG_VOQQMASK_11_LSB 0x168298 2902 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2903 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 2904 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2905 #define QM_REG_VOQQMASK_11_MSB 0x16829c 2906 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2907 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 2908 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2909 #define QM_REG_VOQQMASK_1_LSB 0x168248 2910 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2911 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 2912 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2913 #define QM_REG_VOQQMASK_1_MSB 0x16824c 2914 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2915 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 2916 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2917 #define QM_REG_VOQQMASK_2_LSB 0x168250 2918 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2919 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 2920 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2921 #define QM_REG_VOQQMASK_2_MSB 0x168254 2922 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2923 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 2924 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2925 #define QM_REG_VOQQMASK_3_LSB 0x168258 2926 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2927 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 2928 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2929 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 2930 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2931 #define QM_REG_VOQQMASK_4_LSB 0x168260 2932 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2933 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 2934 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2935 #define QM_REG_VOQQMASK_4_MSB 0x168264 2936 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2937 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 2938 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2939 #define QM_REG_VOQQMASK_5_LSB 0x168268 2940 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2941 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 2942 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2943 #define QM_REG_VOQQMASK_5_MSB 0x16826c 2944 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2945 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 2946 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2947 #define QM_REG_VOQQMASK_6_LSB 0x168270 2948 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2949 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 2950 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2951 #define QM_REG_VOQQMASK_6_MSB 0x168274 2952 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2953 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 2954 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2955 #define QM_REG_VOQQMASK_7_LSB 0x168278 2956 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2957 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 2958 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2959 #define QM_REG_VOQQMASK_7_MSB 0x16827c 2960 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2961 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 2962 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2963 #define QM_REG_VOQQMASK_8_LSB 0x168280 2964 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2965 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 2966 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 2967 #define QM_REG_VOQQMASK_8_MSB 0x168284 2968 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2969 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 2970 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 2971 #define QM_REG_VOQQMASK_9_LSB 0x168288 2972 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 2973 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 2974 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 2975 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 2976 /* [RW 32] Wrr weights */ 2977 #define QM_REG_WRRWEIGHTS_0 0x16880c 2978 #define QM_REG_WRRWEIGHTS_1 0x168810 2979 #define QM_REG_WRRWEIGHTS_10 0x168814 2980 #define QM_REG_WRRWEIGHTS_10_SIZE 1 2981 /* [RW 32] Wrr weights */ 2982 #define QM_REG_WRRWEIGHTS_11 0x168818 2983 #define QM_REG_WRRWEIGHTS_11_SIZE 1 2984 /* [RW 32] Wrr weights */ 2985 #define QM_REG_WRRWEIGHTS_12 0x16881c 2986 #define QM_REG_WRRWEIGHTS_12_SIZE 1 2987 /* [RW 32] Wrr weights */ 2988 #define QM_REG_WRRWEIGHTS_13 0x168820 2989 #define QM_REG_WRRWEIGHTS_13_SIZE 1 2990 /* [RW 32] Wrr weights */ 2991 #define QM_REG_WRRWEIGHTS_14 0x168824 2992 #define QM_REG_WRRWEIGHTS_14_SIZE 1 2993 /* [RW 32] Wrr weights */ 2994 #define QM_REG_WRRWEIGHTS_15 0x168828 2995 #define QM_REG_WRRWEIGHTS_15_SIZE 1 2996 /* [RW 32] Wrr weights */ 2997 #define QM_REG_WRRWEIGHTS_16 0x16e000 2998 #define QM_REG_WRRWEIGHTS_16_SIZE 1 2999 /* [RW 32] Wrr weights */ 3000 #define QM_REG_WRRWEIGHTS_17 0x16e004 3001 #define QM_REG_WRRWEIGHTS_17_SIZE 1 3002 /* [RW 32] Wrr weights */ 3003 #define QM_REG_WRRWEIGHTS_18 0x16e008 3004 #define QM_REG_WRRWEIGHTS_18_SIZE 1 3005 /* [RW 32] Wrr weights */ 3006 #define QM_REG_WRRWEIGHTS_19 0x16e00c 3007 #define QM_REG_WRRWEIGHTS_19_SIZE 1 3008 /* [RW 32] Wrr weights */ 3009 #define QM_REG_WRRWEIGHTS_10 0x168814 3010 #define QM_REG_WRRWEIGHTS_11 0x168818 3011 #define QM_REG_WRRWEIGHTS_12 0x16881c 3012 #define QM_REG_WRRWEIGHTS_13 0x168820 3013 #define QM_REG_WRRWEIGHTS_14 0x168824 3014 #define QM_REG_WRRWEIGHTS_15 0x168828 3015 #define QM_REG_WRRWEIGHTS_16 0x16e000 3016 #define QM_REG_WRRWEIGHTS_17 0x16e004 3017 #define QM_REG_WRRWEIGHTS_18 0x16e008 3018 #define QM_REG_WRRWEIGHTS_19 0x16e00c 3019 #define QM_REG_WRRWEIGHTS_2 0x16882c 3020 #define QM_REG_WRRWEIGHTS_20 0x16e010 3021 #define QM_REG_WRRWEIGHTS_20_SIZE 1 3022 /* [RW 32] Wrr weights */ 3023 #define QM_REG_WRRWEIGHTS_21 0x16e014 3024 #define QM_REG_WRRWEIGHTS_21_SIZE 1 3025 /* [RW 32] Wrr weights */ 3026 #define QM_REG_WRRWEIGHTS_22 0x16e018 3027 #define QM_REG_WRRWEIGHTS_22_SIZE 1 3028 /* [RW 32] Wrr weights */ 3029 #define QM_REG_WRRWEIGHTS_23 0x16e01c 3030 #define QM_REG_WRRWEIGHTS_23_SIZE 1 3031 /* [RW 32] Wrr weights */ 3032 #define QM_REG_WRRWEIGHTS_24 0x16e020 3033 #define QM_REG_WRRWEIGHTS_24_SIZE 1 3034 /* [RW 32] Wrr weights */ 3035 #define QM_REG_WRRWEIGHTS_25 0x16e024 3036 #define QM_REG_WRRWEIGHTS_25_SIZE 1 3037 /* [RW 32] Wrr weights */ 3038 #define QM_REG_WRRWEIGHTS_26 0x16e028 3039 #define QM_REG_WRRWEIGHTS_26_SIZE 1 3040 /* [RW 32] Wrr weights */ 3041 #define QM_REG_WRRWEIGHTS_27 0x16e02c 3042 #define QM_REG_WRRWEIGHTS_27_SIZE 1 3043 /* [RW 32] Wrr weights */ 3044 #define QM_REG_WRRWEIGHTS_28 0x16e030 3045 #define QM_REG_WRRWEIGHTS_28_SIZE 1 3046 /* [RW 32] Wrr weights */ 3047 #define QM_REG_WRRWEIGHTS_29 0x16e034 3048 #define QM_REG_WRRWEIGHTS_29_SIZE 1 3049 /* [RW 32] Wrr weights */ 3050 #define QM_REG_WRRWEIGHTS_20 0x16e010 3051 #define QM_REG_WRRWEIGHTS_21 0x16e014 3052 #define QM_REG_WRRWEIGHTS_22 0x16e018 3053 #define QM_REG_WRRWEIGHTS_23 0x16e01c 3054 #define QM_REG_WRRWEIGHTS_24 0x16e020 3055 #define QM_REG_WRRWEIGHTS_25 0x16e024 3056 #define QM_REG_WRRWEIGHTS_26 0x16e028 3057 #define QM_REG_WRRWEIGHTS_27 0x16e02c 3058 #define QM_REG_WRRWEIGHTS_28 0x16e030 3059 #define QM_REG_WRRWEIGHTS_29 0x16e034 3060 #define QM_REG_WRRWEIGHTS_3 0x168830 3061 #define QM_REG_WRRWEIGHTS_30 0x16e038 3062 #define QM_REG_WRRWEIGHTS_30_SIZE 1 3063 /* [RW 32] Wrr weights */ 3064 #define QM_REG_WRRWEIGHTS_31 0x16e03c 3065 #define QM_REG_WRRWEIGHTS_31_SIZE 1 3066 /* [RW 32] Wrr weights */ 3067 #define QM_REG_WRRWEIGHTS_30 0x16e038 3068 #define QM_REG_WRRWEIGHTS_31 0x16e03c 3069 #define QM_REG_WRRWEIGHTS_4 0x168834 3070 #define QM_REG_WRRWEIGHTS_5 0x168838 3071 #define QM_REG_WRRWEIGHTS_6 0x16883c 3072 #define QM_REG_WRRWEIGHTS_7 0x168840 3073 #define QM_REG_WRRWEIGHTS_8 0x168844 3074 #define QM_REG_WRRWEIGHTS_9 0x168848 3075 /* [R 6] Keep the fill level of the fifo from write client 1 */ 3076 #define QM_REG_XQM_WRC_FIFOLVL 0x168000 3077 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3078 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3079 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3080 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3081 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3082 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3083 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3084 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3085 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3086 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3087 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3088 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3089 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3090 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3091 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3092 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3093 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3094 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3095 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3096 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3097 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3098 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3099 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3100 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3101 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3102 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3103 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3104 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3105 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3106 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3107 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3108 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3109 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3110 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3111 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3112 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3113 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3114 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3115 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3116 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3117 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3118 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3119 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3120 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3121 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3122 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3123 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3124 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3125 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3126 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3127 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3128 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3129 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3130 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3131 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3132 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3133 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3134 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3135 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3136 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3137 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3138 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3139 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3140 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3141 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3142 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3143 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3144 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3145 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3146 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3147 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3148 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3149 #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3150 #define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3151 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3152 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3153 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3154 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3155 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3156 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3157 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3158 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3159 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3160 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3161 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3162 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3163 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3164 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3165 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3166 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3167 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3168 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3169 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3170 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3171 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3172 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3173 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3174 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3175 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3176 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3177 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3178 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3179 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3180 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3181 #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3182 #define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3183 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3184 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3185 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3186 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3187 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3188 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3189 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3190 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3191 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3192 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3193 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3194 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3195 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3196 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3197 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3198 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3199 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3200 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3201 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3202 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3203 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3204 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3205 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3206 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3207 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3208 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3209 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3210 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3211 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3212 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3213 #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3214 #define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3215 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3216 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3217 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3218 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3219 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3220 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3221 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3222 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3223 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3224 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3225 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3226 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3227 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3228 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3229 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3230 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3231 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3232 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3233 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3234 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3235 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3236 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3237 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3238 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3239 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3240 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3241 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3242 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3243 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3244 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3245 #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3246 #define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3247 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3248 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3249 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3250 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3251 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3252 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3253 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3254 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3255 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3256 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3257 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3258 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3259 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3260 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3261 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3262 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3263 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3264 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3265 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3266 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3267 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3268 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3269 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3270 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3271 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3272 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3273 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3274 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3275 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3276 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3277 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3278 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3279 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3280 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3281 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3282 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3283 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3284 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3285 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3286 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3287 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3288 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3289 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3290 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3291 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3292 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3293 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3294 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3295 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3296 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0 3297 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0) 3298 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3299 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3300 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3301 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3302 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3303 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3304 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3305 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3306 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3307 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3308 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3309 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3310 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3311 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3312 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0 3313 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0) 3314 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3315 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3316 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3317 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) 3318 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 3319 /* [R 1] debug only: This bit indicates whether indicates that external 3320 buffer was wrapped (oldest data was thrown); Relevant only when 3321 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ 3322 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 3323 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 3324 /* [R 1] debug only: This bit indicates whether the internal buffer was 3325 wrapped (oldest data was thrown) Relevant only when 3326 ~dbg_registers_debug_target=0 (internal buffer) */ 3327 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 3328 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1 3329 #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8) 3330 #define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8 3331 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8) 3332 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8 3333 #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8) 3334 #define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8 3335 #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8) 3336 #define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8 3337 /* [RW 32] Wrr weights */ 3338 #define QM_REG_WRRWEIGHTS_0 0x16880c 3339 #define QM_REG_WRRWEIGHTS_0_SIZE 1 3340 /* [RW 32] Wrr weights */ 3341 #define QM_REG_WRRWEIGHTS_1 0x168810 3342 #define QM_REG_WRRWEIGHTS_1_SIZE 1 3343 /* [RW 32] Wrr weights */ 3344 #define QM_REG_WRRWEIGHTS_10 0x168814 3345 #define QM_REG_WRRWEIGHTS_10_SIZE 1 3346 /* [RW 32] Wrr weights */ 3347 #define QM_REG_WRRWEIGHTS_11 0x168818 3348 #define QM_REG_WRRWEIGHTS_11_SIZE 1 3349 /* [RW 32] Wrr weights */ 3350 #define QM_REG_WRRWEIGHTS_12 0x16881c 3351 #define QM_REG_WRRWEIGHTS_12_SIZE 1 3352 /* [RW 32] Wrr weights */ 3353 #define QM_REG_WRRWEIGHTS_13 0x168820 3354 #define QM_REG_WRRWEIGHTS_13_SIZE 1 3355 /* [RW 32] Wrr weights */ 3356 #define QM_REG_WRRWEIGHTS_14 0x168824 3357 #define QM_REG_WRRWEIGHTS_14_SIZE 1 3358 /* [RW 32] Wrr weights */ 3359 #define QM_REG_WRRWEIGHTS_15 0x168828 3360 #define QM_REG_WRRWEIGHTS_15_SIZE 1 3361 /* [RW 32] Wrr weights */ 3362 #define QM_REG_WRRWEIGHTS_2 0x16882c 3363 #define QM_REG_WRRWEIGHTS_2_SIZE 1 3364 /* [RW 32] Wrr weights */ 3365 #define QM_REG_WRRWEIGHTS_3 0x168830 3366 #define QM_REG_WRRWEIGHTS_3_SIZE 1 3367 /* [RW 32] Wrr weights */ 3368 #define QM_REG_WRRWEIGHTS_4 0x168834 3369 #define QM_REG_WRRWEIGHTS_4_SIZE 1 3370 /* [RW 32] Wrr weights */ 3371 #define QM_REG_WRRWEIGHTS_5 0x168838 3372 #define QM_REG_WRRWEIGHTS_5_SIZE 1 3373 /* [RW 32] Wrr weights */ 3374 #define QM_REG_WRRWEIGHTS_6 0x16883c 3375 #define QM_REG_WRRWEIGHTS_6_SIZE 1 3376 /* [RW 32] Wrr weights */ 3377 #define QM_REG_WRRWEIGHTS_7 0x168840 3378 #define QM_REG_WRRWEIGHTS_7_SIZE 1 3379 /* [RW 32] Wrr weights */ 3380 #define QM_REG_WRRWEIGHTS_8 0x168844 3381 #define QM_REG_WRRWEIGHTS_8_SIZE 1 3382 /* [RW 32] Wrr weights */ 3383 #define QM_REG_WRRWEIGHTS_9 0x168848 3384 #define QM_REG_WRRWEIGHTS_9_SIZE 1 3385 /* [RW 32] Wrr weights */ 3386 #define QM_REG_WRRWEIGHTS_16 0x16e000 3387 #define QM_REG_WRRWEIGHTS_16_SIZE 1 3388 /* [RW 32] Wrr weights */ 3389 #define QM_REG_WRRWEIGHTS_17 0x16e004 3390 #define QM_REG_WRRWEIGHTS_17_SIZE 1 3391 /* [RW 32] Wrr weights */ 3392 #define QM_REG_WRRWEIGHTS_18 0x16e008 3393 #define QM_REG_WRRWEIGHTS_18_SIZE 1 3394 /* [RW 32] Wrr weights */ 3395 #define QM_REG_WRRWEIGHTS_19 0x16e00c 3396 #define QM_REG_WRRWEIGHTS_19_SIZE 1 3397 /* [RW 32] Wrr weights */ 3398 #define QM_REG_WRRWEIGHTS_20 0x16e010 3399 #define QM_REG_WRRWEIGHTS_20_SIZE 1 3400 /* [RW 32] Wrr weights */ 3401 #define QM_REG_WRRWEIGHTS_21 0x16e014 3402 #define QM_REG_WRRWEIGHTS_21_SIZE 1 3403 /* [RW 32] Wrr weights */ 3404 #define QM_REG_WRRWEIGHTS_22 0x16e018 3405 #define QM_REG_WRRWEIGHTS_22_SIZE 1 3406 /* [RW 32] Wrr weights */ 3407 #define QM_REG_WRRWEIGHTS_23 0x16e01c 3408 #define QM_REG_WRRWEIGHTS_23_SIZE 1 3409 /* [RW 32] Wrr weights */ 3410 #define QM_REG_WRRWEIGHTS_24 0x16e020 3411 #define QM_REG_WRRWEIGHTS_24_SIZE 1 3412 /* [RW 32] Wrr weights */ 3413 #define QM_REG_WRRWEIGHTS_25 0x16e024 3414 #define QM_REG_WRRWEIGHTS_25_SIZE 1 3415 /* [RW 32] Wrr weights */ 3416 #define QM_REG_WRRWEIGHTS_26 0x16e028 3417 #define QM_REG_WRRWEIGHTS_26_SIZE 1 3418 /* [RW 32] Wrr weights */ 3419 #define QM_REG_WRRWEIGHTS_27 0x16e02c 3420 #define QM_REG_WRRWEIGHTS_27_SIZE 1 3421 /* [RW 32] Wrr weights */ 3422 #define QM_REG_WRRWEIGHTS_28 0x16e030 3423 #define QM_REG_WRRWEIGHTS_28_SIZE 1 3424 /* [RW 32] Wrr weights */ 3425 #define QM_REG_WRRWEIGHTS_29 0x16e034 3426 #define QM_REG_WRRWEIGHTS_29_SIZE 1 3427 /* [RW 32] Wrr weights */ 3428 #define QM_REG_WRRWEIGHTS_30 0x16e038 3429 #define QM_REG_WRRWEIGHTS_30_SIZE 1 3430 /* [RW 32] Wrr weights */ 3431 #define QM_REG_WRRWEIGHTS_31 0x16e03c 3432 #define QM_REG_WRRWEIGHTS_31_SIZE 1 3433 #define SRC_REG_COUNTFREE0 0x40500 3434 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 3435 ports. If set the searcher support 8 functions. */ 3436 #define SRC_REG_E1HMF_ENABLE 0x404cc 3437 #define SRC_REG_FIRSTFREE0 0x40510 3438 #define SRC_REG_KEYRSS0_0 0x40408 3439 #define SRC_REG_KEYRSS0_7 0x40424 3440 #define SRC_REG_KEYRSS1_9 0x40454 3441 #define SRC_REG_LASTFREE0 0x40530 3442 #define SRC_REG_NUMBER_HASH_BITS0 0x40400 3443 /* [RW 1] Reset internal state machines. */ 3444 #define SRC_REG_SOFT_RST 0x4049c 3445 /* [R 3] Interrupt register #0 read */ 3446 #define SRC_REG_SRC_INT_STS 0x404ac 3447 /* [RW 3] Parity mask register #0 read/write */ 3448 #define SRC_REG_SRC_PRTY_MASK 0x404c8 3449 /* [R 3] Parity register #0 read */ 3450 #define SRC_REG_SRC_PRTY_STS 0x404bc 3451 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 3452 #define TCM_REG_CAM_OCCUP 0x5017c 3453 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 3454 disregarded; valid output is deasserted; all other signals are treated as 3455 usual; if 1 - normal activity. */ 3456 #define TCM_REG_CDU_AG_RD_IFEN 0x50034 3457 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 3458 are disregarded; all other signals are treated as usual; if 1 - normal 3459 activity. */ 3460 #define TCM_REG_CDU_AG_WR_IFEN 0x50030 3461 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 3462 disregarded; valid output is deasserted; all other signals are treated as 3463 usual; if 1 - normal activity. */ 3464 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c 3465 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 3466 input is disregarded; all other signals are treated as usual; if 1 - 3467 normal activity. */ 3468 #define TCM_REG_CDU_SM_WR_IFEN 0x50038 3469 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 3470 the initial credit value; read returns the current value of the credit 3471 counter. Must be initialized to 1 at start-up. */ 3472 #define TCM_REG_CFC_INIT_CRD 0x50204 3473 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 3474 weight 8 (the most prioritised); 1 stands for weight 1(least 3475 prioritised); 2 stands for weight 2; tc. */ 3476 #define TCM_REG_CP_WEIGHT 0x500c0 3477 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 3478 disregarded; acknowledge output is deasserted; all other signals are 3479 treated as usual; if 1 - normal activity. */ 3480 #define TCM_REG_CSEM_IFEN 0x5002c 3481 /* [RC 1] Message length mismatch (relative to last indication) at the In#9 3482 interface. */ 3483 #define TCM_REG_CSEM_LENGTH_MIS 0x50174 3484 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 3485 #define TCM_REG_ERR_EVNT_ID 0x500a0 3486 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 3487 #define TCM_REG_ERR_TCM_HDR 0x5009c 3488 /* [RW 8] The Event ID for Timers expiration. */ 3489 #define TCM_REG_EXPR_EVNT_ID 0x500a4 3490 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 3491 writes the initial credit value; read returns the current value of the 3492 credit counter. Must be initialized to 64 at start-up. */ 3493 #define TCM_REG_FIC0_INIT_CRD 0x5020c 3494 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 3495 writes the initial credit value; read returns the current value of the 3496 credit counter. Must be initialized to 64 at start-up. */ 3497 #define TCM_REG_FIC1_INIT_CRD 0x50210 3498 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 3499 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 3500 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 3501 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 3502 #define TCM_REG_GR_ARB_TYPE 0x50114 3503 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 3504 highest priority is 3. It is supposed that the Store channel is the 3505 compliment of the other 3 groups. */ 3506 #define TCM_REG_GR_LD0_PR 0x5011c 3507 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 3508 highest priority is 3. It is supposed that the Store channel is the 3509 compliment of the other 3 groups. */ 3510 #define TCM_REG_GR_LD1_PR 0x50120 3511 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and 3512 sent to STORM; for a specific connection type. The double REG-pairs are 3513 used to align to STORM context row size of 128 bits. The offset of these 3514 data in the STORM context is always 0. Index _i stands for the connection 3515 type (one of 16). */ 3516 #define TCM_REG_N_SM_CTX_LD_0 0x50050 3517 #define TCM_REG_N_SM_CTX_LD_1 0x50054 3518 #define TCM_REG_N_SM_CTX_LD_10 0x50078 3519 #define TCM_REG_N_SM_CTX_LD_11 0x5007c 3520 #define TCM_REG_N_SM_CTX_LD_12 0x50080 3521 #define TCM_REG_N_SM_CTX_LD_13 0x50084 3522 #define TCM_REG_N_SM_CTX_LD_14 0x50088 3523 #define TCM_REG_N_SM_CTX_LD_15 0x5008c 3524 #define TCM_REG_N_SM_CTX_LD_2 0x50058 3525 #define TCM_REG_N_SM_CTX_LD_3 0x5005c 3526 #define TCM_REG_N_SM_CTX_LD_4 0x50060 3527 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 3528 acknowledge output is deasserted; all other signals are treated as usual; 3529 if 1 - normal activity. */ 3530 #define TCM_REG_PBF_IFEN 0x50024 3531 /* [RC 1] Message length mismatch (relative to last indication) at the In#7 3532 interface. */ 3533 #define TCM_REG_PBF_LENGTH_MIS 0x5016c 3534 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 3535 weight 8 (the most prioritised); 1 stands for weight 1(least 3536 prioritised); 2 stands for weight 2; tc. */ 3537 #define TCM_REG_PBF_WEIGHT 0x500b4 3538 #define TCM_REG_PHYS_QNUM0_0 0x500e0 3539 #define TCM_REG_PHYS_QNUM0_1 0x500e4 3540 #define TCM_REG_PHYS_QNUM1_0 0x500e8 3541 #define TCM_REG_PHYS_QNUM1_1 0x500ec 3542 #define TCM_REG_PHYS_QNUM2_0 0x500f0 3543 #define TCM_REG_PHYS_QNUM2_1 0x500f4 3544 #define TCM_REG_PHYS_QNUM3_0 0x500f8 3545 #define TCM_REG_PHYS_QNUM3_1 0x500fc 3546 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 3547 acknowledge output is deasserted; all other signals are treated as usual; 3548 if 1 - normal activity. */ 3549 #define TCM_REG_PRS_IFEN 0x50020 3550 /* [RC 1] Message length mismatch (relative to last indication) at the In#6 3551 interface. */ 3552 #define TCM_REG_PRS_LENGTH_MIS 0x50168 3553 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 3554 weight 8 (the most prioritised); 1 stands for weight 1(least 3555 prioritised); 2 stands for weight 2; tc. */ 3556 #define TCM_REG_PRS_WEIGHT 0x500b0 3557 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 3558 #define TCM_REG_STOP_EVNT_ID 0x500a8 3559 /* [RC 1] Message length mismatch (relative to last indication) at the STORM 3560 interface. */ 3561 #define TCM_REG_STORM_LENGTH_MIS 0x50160 3562 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 3563 disregarded; acknowledge output is deasserted; all other signals are 3564 treated as usual; if 1 - normal activity. */ 3565 #define TCM_REG_STORM_TCM_IFEN 0x50010 3566 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 3567 acknowledge output is deasserted; all other signals are treated as usual; 3568 if 1 - normal activity. */ 3569 #define TCM_REG_TCM_CFC_IFEN 0x50040 3570 /* [RW 11] Interrupt mask register #0 read/write */ 3571 #define TCM_REG_TCM_INT_MASK 0x501dc 3572 /* [R 11] Interrupt register #0 read */ 3573 #define TCM_REG_TCM_INT_STS 0x501d0 3574 /* [R 27] Parity register #0 read */ 3575 #define TCM_REG_TCM_PRTY_STS 0x501e0 3576 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 3577 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 3578 Is used to determine the number of the AG context REG-pairs written back; 3579 when the input message Reg1WbFlg isn't set. */ 3580 #define TCM_REG_TCM_REG0_SZ 0x500d8 3581 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 3582 disregarded; valid is deasserted; all other signals are treated as usual; 3583 if 1 - normal activity. */ 3584 #define TCM_REG_TCM_STORM0_IFEN 0x50004 3585 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 3586 disregarded; valid is deasserted; all other signals are treated as usual; 3587 if 1 - normal activity. */ 3588 #define TCM_REG_TCM_STORM1_IFEN 0x50008 3589 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 3590 disregarded; valid is deasserted; all other signals are treated as usual; 3591 if 1 - normal activity. */ 3592 #define TCM_REG_TCM_TQM_IFEN 0x5000c 3593 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 3594 #define TCM_REG_TCM_TQM_USE_Q 0x500d4 3595 /* [RW 28] The CM header for Timers expiration command. */ 3596 #define TCM_REG_TM_TCM_HDR 0x50098 3597 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 3598 disregarded; acknowledge output is deasserted; all other signals are 3599 treated as usual; if 1 - normal activity. */ 3600 #define TCM_REG_TM_TCM_IFEN 0x5001c 3601 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 3602 the initial credit value; read returns the current value of the credit 3603 counter. Must be initialized to 32 at start-up. */ 3604 #define TCM_REG_TQM_INIT_CRD 0x5021c 3605 /* [RW 28] The CM header value for QM request (primary). */ 3606 #define TCM_REG_TQM_TCM_HDR_P 0x50090 3607 /* [RW 28] The CM header value for QM request (secondary). */ 3608 #define TCM_REG_TQM_TCM_HDR_S 0x50094 3609 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 3610 acknowledge output is deasserted; all other signals are treated as usual; 3611 if 1 - normal activity. */ 3612 #define TCM_REG_TQM_TCM_IFEN 0x50014 3613 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 3614 acknowledge output is deasserted; all other signals are treated as usual; 3615 if 1 - normal activity. */ 3616 #define TCM_REG_TSDM_IFEN 0x50018 3617 /* [RC 1] Message length mismatch (relative to last indication) at the SDM 3618 interface. */ 3619 #define TCM_REG_TSDM_LENGTH_MIS 0x50164 3620 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 3621 weight 8 (the most prioritised); 1 stands for weight 1(least 3622 prioritised); 2 stands for weight 2; tc. */ 3623 #define TCM_REG_TSDM_WEIGHT 0x500c4 3624 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 3625 disregarded; acknowledge output is deasserted; all other signals are 3626 treated as usual; if 1 - normal activity. */ 3627 #define TCM_REG_USEM_IFEN 0x50028 3628 /* [RC 1] Message length mismatch (relative to last indication) at the In#8 3629 interface. */ 3630 #define TCM_REG_USEM_LENGTH_MIS 0x50170 3631 /* [RW 21] Indirect access to the descriptor table of the XX protection 3632 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 3633 pointer; 20:16] - next pointer. */ 3634 #define TCM_REG_XX_DESCR_TABLE 0x50280 3635 #define TCM_REG_XX_DESCR_TABLE_SIZE 32 3636 /* [R 6] Use to read the value of XX protection Free counter. */ 3637 #define TCM_REG_XX_FREE 0x50178 3638 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 3639 of the Input Stage XX protection buffer by the XX protection pending 3640 messages. Max credit available - 127.Write writes the initial credit 3641 value; read returns the current value of the credit counter. Must be 3642 initialized to 19 at start-up. */ 3643 #define TCM_REG_XX_INIT_CRD 0x50220 3644 /* [RW 6] Maximum link list size (messages locked) per connection in the XX 3645 protection. */ 3646 #define TCM_REG_XX_MAX_LL_SZ 0x50044 3647 /* [RW 6] The maximum number of pending messages; which may be stored in XX 3648 protection. ~tcm_registers_xx_free.xx_free is read on read. */ 3649 #define TCM_REG_XX_MSG_NUM 0x50224 3650 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 3651 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048 3652 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 3653 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 3654 header pointer. */ 3655 #define TCM_REG_XX_TABLE 0x50240 3656 /* [RW 4] Load value for for cfc ac credit cnt. */ 3657 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 3658 /* [RW 4] Load value for cfc cld credit cnt. */ 3659 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 3660 /* [RW 8] Client0 context region. */ 3661 #define TM_REG_CL0_CONT_REGION 0x164030 3662 /* [RW 8] Client1 context region. */ 3663 #define TM_REG_CL1_CONT_REGION 0x164034 3664 /* [RW 8] Client2 context region. */ 3665 #define TM_REG_CL2_CONT_REGION 0x164038 3666 /* [RW 2] Client in High priority client number. */ 3667 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 3668 /* [RW 4] Load value for clout0 cred cnt. */ 3669 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 3670 /* [RW 4] Load value for clout1 cred cnt. */ 3671 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 3672 /* [RW 4] Load value for clout2 cred cnt. */ 3673 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 3674 /* [RW 1] Enable client0 input. */ 3675 #define TM_REG_EN_CL0_INPUT 0x164008 3676 /* [RW 1] Enable client1 input. */ 3677 #define TM_REG_EN_CL1_INPUT 0x16400c 3678 /* [RW 1] Enable client2 input. */ 3679 #define TM_REG_EN_CL2_INPUT 0x164010 3680 /* [RW 1] Enable real time counter. */ 3681 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8 3682 /* [RW 1] Enable for Timers state machines. */ 3683 #define TM_REG_EN_TIMERS 0x164000 3684 /* [RW 4] Load value for expiration credit cnt. CFC max number of 3685 outstanding load requests for timers (expiration) context loading. */ 3686 #define TM_REG_EXP_CRDCNT_VAL 0x164238 3687 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 3688 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 3689 /* [WB 64] Linear0 phy address. */ 3690 #define TM_REG_LIN0_PHY_ADDR 0x164270 3691 /* [RW 24] Linear0 array scan timeout. */ 3692 #define TM_REG_LIN0_SCAN_TIME 0x16403c 3693 /* [WB 64] Linear1 phy address. */ 3694 #define TM_REG_LIN1_PHY_ADDR 0x164280 3695 /* [RW 6] Linear timer set_clear fifo threshold. */ 3696 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 3697 /* [RW 2] Load value for pci arbiter credit cnt. */ 3698 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260 3699 /* [RW 1] Timer software reset - active high. */ 3700 #define TM_REG_TIMER_SOFT_RST 0x164004 3701 /* [RW 20] The amount of hardware cycles for each timer tick. */ 3702 #define TM_REG_TIMER_TICK_SIZE 0x16401c 3703 /* [RW 8] Timers Context region. */ 3704 #define TM_REG_TM_CONTEXT_REGION 0x164044 3705 /* [RW 1] Interrupt mask register #0 read/write */ 3706 #define TM_REG_TM_INT_MASK 0x1640fc 3707 /* [R 1] Interrupt register #0 read */ 3708 #define TM_REG_TM_INT_STS 0x1640f0 3709 /* [RW 8] The event id for aggregated interrupt 0 */ 3710 #define TSDM_REG_AGG_INT_EVENT_0 0x42038 3711 #define TSDM_REG_AGG_INT_EVENT_2 0x42040 3712 #define TSDM_REG_AGG_INT_EVENT_20 0x42088 3713 #define TSDM_REG_AGG_INT_EVENT_21 0x4208c 3714 #define TSDM_REG_AGG_INT_EVENT_22 0x42090 3715 #define TSDM_REG_AGG_INT_EVENT_23 0x42094 3716 #define TSDM_REG_AGG_INT_EVENT_24 0x42098 3717 #define TSDM_REG_AGG_INT_EVENT_25 0x4209c 3718 #define TSDM_REG_AGG_INT_EVENT_26 0x420a0 3719 #define TSDM_REG_AGG_INT_EVENT_27 0x420a4 3720 #define TSDM_REG_AGG_INT_EVENT_28 0x420a8 3721 #define TSDM_REG_AGG_INT_EVENT_29 0x420ac 3722 #define TSDM_REG_AGG_INT_EVENT_3 0x42044 3723 #define TSDM_REG_AGG_INT_EVENT_30 0x420b0 3724 #define TSDM_REG_AGG_INT_EVENT_31 0x420b4 3725 #define TSDM_REG_AGG_INT_EVENT_4 0x42048 3726 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 3727 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008 3728 /* [RW 16] The maximum value of the competion counter #0 */ 3729 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 3730 /* [RW 16] The maximum value of the competion counter #1 */ 3731 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020 3732 /* [RW 16] The maximum value of the competion counter #2 */ 3733 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024 3734 /* [RW 16] The maximum value of the competion counter #3 */ 3735 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028 3736 /* [RW 13] The start address in the internal RAM for the completion 3737 counters. */ 3738 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 3739 #define TSDM_REG_ENABLE_IN1 0x42238 3740 #define TSDM_REG_ENABLE_IN2 0x4223c 3741 #define TSDM_REG_ENABLE_OUT1 0x42240 3742 #define TSDM_REG_ENABLE_OUT2 0x42244 3743 /* [RW 4] The initial number of messages that can be sent to the pxp control 3744 interface without receiving any ACK. */ 3745 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 3746 /* [ST 32] The number of ACK after placement messages received */ 3747 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 3748 /* [ST 32] The number of packet end messages received from the parser */ 3749 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 3750 /* [ST 32] The number of requests received from the pxp async if */ 3751 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 3752 /* [ST 32] The number of commands received in queue 0 */ 3753 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248 3754 /* [ST 32] The number of commands received in queue 10 */ 3755 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 3756 /* [ST 32] The number of commands received in queue 11 */ 3757 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270 3758 /* [ST 32] The number of commands received in queue 1 */ 3759 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 3760 /* [ST 32] The number of commands received in queue 3 */ 3761 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250 3762 /* [ST 32] The number of commands received in queue 4 */ 3763 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254 3764 /* [ST 32] The number of commands received in queue 5 */ 3765 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258 3766 /* [ST 32] The number of commands received in queue 6 */ 3767 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 3768 /* [ST 32] The number of commands received in queue 7 */ 3769 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260 3770 /* [ST 32] The number of commands received in queue 8 */ 3771 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264 3772 /* [ST 32] The number of commands received in queue 9 */ 3773 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268 3774 /* [RW 13] The start address in the internal RAM for the packet end message */ 3775 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 3776 /* [RW 13] The start address in the internal RAM for queue counters */ 3777 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 3778 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 3779 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 3780 /* [R 1] parser fifo empty in sdm_sync block */ 3781 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 3782 /* [R 1] parser serial fifo empty in sdm_sync block */ 3783 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 3784 /* [RW 32] Tick for timer counter. Applicable only when 3785 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 3786 #define TSDM_REG_TIMER_TICK 0x42000 3787 /* [RW 32] Interrupt mask register #0 read/write */ 3788 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c 3789 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac 3790 /* [R 32] Interrupt register #0 read */ 3791 #define TSDM_REG_TSDM_INT_STS_0 0x42290 3792 #define TSDM_REG_TSDM_INT_STS_1 0x422a0 3793 /* [RW 11] Parity mask register #0 read/write */ 3794 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc 3795 /* [R 11] Parity register #0 read */ 3796 #define TSDM_REG_TSDM_PRTY_STS 0x422b0 3797 /* [RW 5] The number of time_slots in the arbitration cycle */ 3798 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 3799 /* [RW 3] The source that is associated with arbitration element 0. Source 3800 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 3801 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 3802 #define TSEM_REG_ARB_ELEMENT0 0x180020 3803 /* [RW 3] The source that is associated with arbitration element 1. Source 3804 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 3805 sleeping thread with priority 1; 4- sleeping thread with priority 2. 3806 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 3807 #define TSEM_REG_ARB_ELEMENT1 0x180024 3808 /* [RW 3] The source that is associated with arbitration element 2. Source 3809 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 3810 sleeping thread with priority 1; 4- sleeping thread with priority 2. 3811 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 3812 and ~tsem_registers_arb_element1.arb_element1 */ 3813 #define TSEM_REG_ARB_ELEMENT2 0x180028 3814 /* [RW 3] The source that is associated with arbitration element 3. Source 3815 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 3816 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 3817 not be equal to register ~tsem_registers_arb_element0.arb_element0 and 3818 ~tsem_registers_arb_element1.arb_element1 and 3819 ~tsem_registers_arb_element2.arb_element2 */ 3820 #define TSEM_REG_ARB_ELEMENT3 0x18002c 3821 /* [RW 3] The source that is associated with arbitration element 4. Source 3822 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 3823 sleeping thread with priority 1; 4- sleeping thread with priority 2. 3824 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 3825 and ~tsem_registers_arb_element1.arb_element1 and 3826 ~tsem_registers_arb_element2.arb_element2 and 3827 ~tsem_registers_arb_element3.arb_element3 */ 3828 #define TSEM_REG_ARB_ELEMENT4 0x180030 3829 #define TSEM_REG_ENABLE_IN 0x1800a4 3830 #define TSEM_REG_ENABLE_OUT 0x1800a8 3831 /* [RW 32] This address space contains all registers and memories that are 3832 placed in SEM_FAST block. The SEM_FAST registers are described in 3833 appendix B. In order to access the sem_fast registers the base address 3834 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 3835 #define TSEM_REG_FAST_MEMORY 0x1a0000 3836 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 3837 by the microcode */ 3838 #define TSEM_REG_FIC0_DISABLE 0x180224 3839 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 3840 by the microcode */ 3841 #define TSEM_REG_FIC1_DISABLE 0x180234 3842 /* [RW 15] Interrupt table Read and write access to it is not possible in 3843 the middle of the work */ 3844 #define TSEM_REG_INT_TABLE 0x180400 3845 /* [ST 24] Statistics register. The number of messages that entered through 3846 FIC0 */ 3847 #define TSEM_REG_MSG_NUM_FIC0 0x180000 3848 /* [ST 24] Statistics register. The number of messages that entered through 3849 FIC1 */ 3850 #define TSEM_REG_MSG_NUM_FIC1 0x180004 3851 /* [ST 24] Statistics register. The number of messages that were sent to 3852 FOC0 */ 3853 #define TSEM_REG_MSG_NUM_FOC0 0x180008 3854 /* [ST 24] Statistics register. The number of messages that were sent to 3855 FOC1 */ 3856 #define TSEM_REG_MSG_NUM_FOC1 0x18000c 3857 /* [ST 24] Statistics register. The number of messages that were sent to 3858 FOC2 */ 3859 #define TSEM_REG_MSG_NUM_FOC2 0x180010 3860 /* [ST 24] Statistics register. The number of messages that were sent to 3861 FOC3 */ 3862 #define TSEM_REG_MSG_NUM_FOC3 0x180014 3863 /* [RW 1] Disables input messages from the passive buffer May be updated 3864 during run_time by the microcode */ 3865 #define TSEM_REG_PAS_DISABLE 0x18024c 3866 /* [WB 128] Debug only. Passive buffer memory */ 3867 #define TSEM_REG_PASSIVE_BUFFER 0x181000 3868 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 3869 #define TSEM_REG_PRAM 0x1c0000 3870 /* [R 8] Valid sleeping threads indication have bit per thread */ 3871 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 3872 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 3873 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 3874 /* [RW 8] List of free threads . There is a bit per thread. */ 3875 #define TSEM_REG_THREADS_LIST 0x1802e4 3876 /* [RW 3] The arbitration scheme of time_slot 0 */ 3877 #define TSEM_REG_TS_0_AS 0x180038 3878 /* [RW 3] The arbitration scheme of time_slot 10 */ 3879 #define TSEM_REG_TS_10_AS 0x180060 3880 /* [RW 3] The arbitration scheme of time_slot 11 */ 3881 #define TSEM_REG_TS_11_AS 0x180064 3882 /* [RW 3] The arbitration scheme of time_slot 12 */ 3883 #define TSEM_REG_TS_12_AS 0x180068 3884 /* [RW 3] The arbitration scheme of time_slot 13 */ 3885 #define TSEM_REG_TS_13_AS 0x18006c 3886 /* [RW 3] The arbitration scheme of time_slot 14 */ 3887 #define TSEM_REG_TS_14_AS 0x180070 3888 /* [RW 3] The arbitration scheme of time_slot 15 */ 3889 #define TSEM_REG_TS_15_AS 0x180074 3890 /* [RW 3] The arbitration scheme of time_slot 16 */ 3891 #define TSEM_REG_TS_16_AS 0x180078 3892 /* [RW 3] The arbitration scheme of time_slot 17 */ 3893 #define TSEM_REG_TS_17_AS 0x18007c 3894 /* [RW 3] The arbitration scheme of time_slot 18 */ 3895 #define TSEM_REG_TS_18_AS 0x180080 3896 /* [RW 3] The arbitration scheme of time_slot 1 */ 3897 #define TSEM_REG_TS_1_AS 0x18003c 3898 /* [RW 3] The arbitration scheme of time_slot 2 */ 3899 #define TSEM_REG_TS_2_AS 0x180040 3900 /* [RW 3] The arbitration scheme of time_slot 3 */ 3901 #define TSEM_REG_TS_3_AS 0x180044 3902 /* [RW 3] The arbitration scheme of time_slot 4 */ 3903 #define TSEM_REG_TS_4_AS 0x180048 3904 /* [RW 3] The arbitration scheme of time_slot 5 */ 3905 #define TSEM_REG_TS_5_AS 0x18004c 3906 /* [RW 3] The arbitration scheme of time_slot 6 */ 3907 #define TSEM_REG_TS_6_AS 0x180050 3908 /* [RW 3] The arbitration scheme of time_slot 7 */ 3909 #define TSEM_REG_TS_7_AS 0x180054 3910 /* [RW 3] The arbitration scheme of time_slot 8 */ 3911 #define TSEM_REG_TS_8_AS 0x180058 3912 /* [RW 3] The arbitration scheme of time_slot 9 */ 3913 #define TSEM_REG_TS_9_AS 0x18005c 3914 /* [RW 32] Interrupt mask register #0 read/write */ 3915 #define TSEM_REG_TSEM_INT_MASK_0 0x180100 3916 #define TSEM_REG_TSEM_INT_MASK_1 0x180110 3917 /* [R 32] Interrupt register #0 read */ 3918 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 3919 #define TSEM_REG_TSEM_INT_STS_1 0x180104 3920 /* [RW 32] Parity mask register #0 read/write */ 3921 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 3922 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 3923 /* [R 32] Parity register #0 read */ 3924 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 3925 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 3926 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 3927 #define UCM_REG_CAM_OCCUP 0xe0170 3928 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 3929 disregarded; valid output is deasserted; all other signals are treated as 3930 usual; if 1 - normal activity. */ 3931 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038 3932 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 3933 are disregarded; all other signals are treated as usual; if 1 - normal 3934 activity. */ 3935 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034 3936 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 3937 disregarded; valid output is deasserted; all other signals are treated as 3938 usual; if 1 - normal activity. */ 3939 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040 3940 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 3941 input is disregarded; all other signals are treated as usual; if 1 - 3942 normal activity. */ 3943 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c 3944 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 3945 the initial credit value; read returns the current value of the credit 3946 counter. Must be initialized to 1 at start-up. */ 3947 #define UCM_REG_CFC_INIT_CRD 0xe0204 3948 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 3949 weight 8 (the most prioritised); 1 stands for weight 1(least 3950 prioritised); 2 stands for weight 2; tc. */ 3951 #define UCM_REG_CP_WEIGHT 0xe00c4 3952 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 3953 disregarded; acknowledge output is deasserted; all other signals are 3954 treated as usual; if 1 - normal activity. */ 3955 #define UCM_REG_CSEM_IFEN 0xe0028 3956 /* [RC 1] Set when the message length mismatch (relative to last indication) 3957 at the csem interface is detected. */ 3958 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 3959 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 3960 weight 8 (the most prioritised); 1 stands for weight 1(least 3961 prioritised); 2 stands for weight 2; tc. */ 3962 #define UCM_REG_CSEM_WEIGHT 0xe00b8 3963 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 3964 disregarded; acknowledge output is deasserted; all other signals are 3965 treated as usual; if 1 - normal activity. */ 3966 #define UCM_REG_DORQ_IFEN 0xe0030 3967 /* [RC 1] Set when the message length mismatch (relative to last indication) 3968 at the dorq interface is detected. */ 3969 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 3970 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 3971 #define UCM_REG_ERR_EVNT_ID 0xe00a4 3972 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 3973 #define UCM_REG_ERR_UCM_HDR 0xe00a0 3974 /* [RW 8] The Event ID for Timers expiration. */ 3975 #define UCM_REG_EXPR_EVNT_ID 0xe00a8 3976 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 3977 writes the initial credit value; read returns the current value of the 3978 credit counter. Must be initialized to 64 at start-up. */ 3979 #define UCM_REG_FIC0_INIT_CRD 0xe020c 3980 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 3981 writes the initial credit value; read returns the current value of the 3982 credit counter. Must be initialized to 64 at start-up. */ 3983 #define UCM_REG_FIC1_INIT_CRD 0xe0210 3984 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 3985 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 3986 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 3987 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 3988 #define UCM_REG_GR_ARB_TYPE 0xe0144 3989 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 3990 highest priority is 3. It is supposed that the Store channel group is 3991 compliment to the others. */ 3992 #define UCM_REG_GR_LD0_PR 0xe014c 3993 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 3994 highest priority is 3. It is supposed that the Store channel group is 3995 compliment to the others. */ 3996 #define UCM_REG_GR_LD1_PR 0xe0150 3997 /* [RW 2] The queue index for invalidate counter flag decision. */ 3998 #define UCM_REG_INV_CFLG_Q 0xe00e4 3999 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4000 sent to STORM; for a specific connection type. the double REG-pairs are 4001 used in order to align to STORM context row size of 128 bits. The offset 4002 of these data in the STORM context is always 0. Index _i stands for the 4003 connection type (one of 16). */ 4004 #define UCM_REG_N_SM_CTX_LD_0 0xe0054 4005 #define UCM_REG_N_SM_CTX_LD_1 0xe0058 4006 #define UCM_REG_N_SM_CTX_LD_10 0xe007c 4007 #define UCM_REG_N_SM_CTX_LD_11 0xe0080 4008 #define UCM_REG_N_SM_CTX_LD_12 0xe0084 4009 #define UCM_REG_N_SM_CTX_LD_13 0xe0088 4010 #define UCM_REG_N_SM_CTX_LD_14 0xe008c 4011 #define UCM_REG_N_SM_CTX_LD_15 0xe0090 4012 #define UCM_REG_N_SM_CTX_LD_2 0xe005c 4013 #define UCM_REG_N_SM_CTX_LD_3 0xe0060 4014 #define UCM_REG_N_SM_CTX_LD_4 0xe0064 4015 #define UCM_REG_N_SM_CTX_LD_5 0xe0068 4016 #define UCM_REG_PHYS_QNUM0_0 0xe0110 4017 #define UCM_REG_PHYS_QNUM0_1 0xe0114 4018 #define UCM_REG_PHYS_QNUM1_0 0xe0118 4019 #define UCM_REG_PHYS_QNUM1_1 0xe011c 4020 #define UCM_REG_PHYS_QNUM2_0 0xe0120 4021 #define UCM_REG_PHYS_QNUM2_1 0xe0124 4022 #define UCM_REG_PHYS_QNUM3_0 0xe0128 4023 #define UCM_REG_PHYS_QNUM3_1 0xe012c 4024 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4025 #define UCM_REG_STOP_EVNT_ID 0xe00ac 4026 /* [RC 1] Set when the message length mismatch (relative to last indication) 4027 at the STORM interface is detected. */ 4028 #define UCM_REG_STORM_LENGTH_MIS 0xe0154 4029 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4030 disregarded; acknowledge output is deasserted; all other signals are 4031 treated as usual; if 1 - normal activity. */ 4032 #define UCM_REG_STORM_UCM_IFEN 0xe0010 4033 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4034 writes the initial credit value; read returns the current value of the 4035 credit counter. Must be initialized to 4 at start-up. */ 4036 #define UCM_REG_TM_INIT_CRD 0xe021c 4037 /* [RW 28] The CM header for Timers expiration command. */ 4038 #define UCM_REG_TM_UCM_HDR 0xe009c 4039 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4040 disregarded; acknowledge output is deasserted; all other signals are 4041 treated as usual; if 1 - normal activity. */ 4042 #define UCM_REG_TM_UCM_IFEN 0xe001c 4043 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4044 disregarded; acknowledge output is deasserted; all other signals are 4045 treated as usual; if 1 - normal activity. */ 4046 #define UCM_REG_TSEM_IFEN 0xe0024 4047 /* [RC 1] Set when the message length mismatch (relative to last indication) 4048 at the tsem interface is detected. */ 4049 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c 4050 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4051 weight 8 (the most prioritised); 1 stands for weight 1(least 4052 prioritised); 2 stands for weight 2; tc. */ 4053 #define UCM_REG_TSEM_WEIGHT 0xe00b4 4054 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4055 acknowledge output is deasserted; all other signals are treated as usual; 4056 if 1 - normal activity. */ 4057 #define UCM_REG_UCM_CFC_IFEN 0xe0044 4058 /* [RW 11] Interrupt mask register #0 read/write */ 4059 #define UCM_REG_UCM_INT_MASK 0xe01d4 4060 /* [R 11] Interrupt register #0 read */ 4061 #define UCM_REG_UCM_INT_STS 0xe01c8 4062 /* [R 27] Parity register #0 read */ 4063 #define UCM_REG_UCM_PRTY_STS 0xe01d8 4064 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4065 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4066 Is used to determine the number of the AG context REG-pairs written back; 4067 when the Reg1WbFlg isn't set. */ 4068 #define UCM_REG_UCM_REG0_SZ 0xe00dc 4069 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4070 disregarded; valid is deasserted; all other signals are treated as usual; 4071 if 1 - normal activity. */ 4072 #define UCM_REG_UCM_STORM0_IFEN 0xe0004 4073 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4074 disregarded; valid is deasserted; all other signals are treated as usual; 4075 if 1 - normal activity. */ 4076 #define UCM_REG_UCM_STORM1_IFEN 0xe0008 4077 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4078 disregarded; acknowledge output is deasserted; all other signals are 4079 treated as usual; if 1 - normal activity. */ 4080 #define UCM_REG_UCM_TM_IFEN 0xe0020 4081 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4082 disregarded; valid is deasserted; all other signals are treated as usual; 4083 if 1 - normal activity. */ 4084 #define UCM_REG_UCM_UQM_IFEN 0xe000c 4085 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4086 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8 4087 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4088 the initial credit value; read returns the current value of the credit 4089 counter. Must be initialized to 32 at start-up. */ 4090 #define UCM_REG_UQM_INIT_CRD 0xe0220 4091 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4092 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4093 prioritised); 2 stands for weight 2; tc. */ 4094 #define UCM_REG_UQM_P_WEIGHT 0xe00cc 4095 /* [RW 28] The CM header value for QM request (primary). */ 4096 #define UCM_REG_UQM_UCM_HDR_P 0xe0094 4097 /* [RW 28] The CM header value for QM request (secondary). */ 4098 #define UCM_REG_UQM_UCM_HDR_S 0xe0098 4099 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4100 acknowledge output is deasserted; all other signals are treated as usual; 4101 if 1 - normal activity. */ 4102 #define UCM_REG_UQM_UCM_IFEN 0xe0014 4103 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4104 acknowledge output is deasserted; all other signals are treated as usual; 4105 if 1 - normal activity. */ 4106 #define UCM_REG_USDM_IFEN 0xe0018 4107 /* [RC 1] Set when the message length mismatch (relative to last indication) 4108 at the SDM interface is detected. */ 4109 #define UCM_REG_USDM_LENGTH_MIS 0xe0158 4110 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is 4111 disregarded; acknowledge output is deasserted; all other signals are 4112 treated as usual; if 1 - normal activity. */ 4113 #define UCM_REG_XSEM_IFEN 0xe002c 4114 /* [RC 1] Set when the message length mismatch (relative to last indication) 4115 at the xsem interface isdetected. */ 4116 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 4117 /* [RW 20] Indirect access to the descriptor table of the XX protection 4118 mechanism. The fields are:[5:0] - message length; 14:6] - message 4119 pointer; 19:15] - next pointer. */ 4120 #define UCM_REG_XX_DESCR_TABLE 0xe0280 4121 #define UCM_REG_XX_DESCR_TABLE_SIZE 32 4122 /* [R 6] Use to read the XX protection Free counter. */ 4123 #define UCM_REG_XX_FREE 0xe016c 4124 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4125 of the Input Stage XX protection buffer by the XX protection pending 4126 messages. Write writes the initial credit value; read returns the current 4127 value of the credit counter. Must be initialized to 12 at start-up. */ 4128 #define UCM_REG_XX_INIT_CRD 0xe0224 4129 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4130 protection. ~ucm_registers_xx_free.xx_free read on read. */ 4131 #define UCM_REG_XX_MSG_NUM 0xe0228 4132 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4133 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 4134 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4135 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4136 header pointer. */ 4137 #define UCM_REG_XX_TABLE 0xe0300 4138 /* [RW 8] The event id for aggregated interrupt 0 */ 4139 #define USDM_REG_AGG_INT_EVENT_0 0xc4038 4140 #define USDM_REG_AGG_INT_EVENT_1 0xc403c 4141 #define USDM_REG_AGG_INT_EVENT_10 0xc4060 4142 #define USDM_REG_AGG_INT_EVENT_11 0xc4064 4143 #define USDM_REG_AGG_INT_EVENT_12 0xc4068 4144 #define USDM_REG_AGG_INT_EVENT_13 0xc406c 4145 #define USDM_REG_AGG_INT_EVENT_14 0xc4070 4146 #define USDM_REG_AGG_INT_EVENT_15 0xc4074 4147 #define USDM_REG_AGG_INT_EVENT_16 0xc4078 4148 #define USDM_REG_AGG_INT_EVENT_17 0xc407c 4149 #define USDM_REG_AGG_INT_EVENT_18 0xc4080 4150 #define USDM_REG_AGG_INT_EVENT_19 0xc4084 4151 #define USDM_REG_AGG_INT_EVENT_2 0xc4040 4152 #define USDM_REG_AGG_INT_EVENT_20 0xc4088 4153 #define USDM_REG_AGG_INT_EVENT_21 0xc408c 4154 #define USDM_REG_AGG_INT_EVENT_22 0xc4090 4155 #define USDM_REG_AGG_INT_EVENT_23 0xc4094 4156 #define USDM_REG_AGG_INT_EVENT_24 0xc4098 4157 #define USDM_REG_AGG_INT_EVENT_25 0xc409c 4158 #define USDM_REG_AGG_INT_EVENT_26 0xc40a0 4159 #define USDM_REG_AGG_INT_EVENT_27 0xc40a4 4160 #define USDM_REG_AGG_INT_EVENT_28 0xc40a8 4161 #define USDM_REG_AGG_INT_EVENT_29 0xc40ac 4162 #define USDM_REG_AGG_INT_EVENT_3 0xc4044 4163 #define USDM_REG_AGG_INT_EVENT_30 0xc40b0 4164 #define USDM_REG_AGG_INT_EVENT_31 0xc40b4 4165 #define USDM_REG_AGG_INT_EVENT_4 0xc4048 4166 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4167 or auto-mask-mode (1) */ 4168 #define USDM_REG_AGG_INT_MODE_0 0xc41b8 4169 #define USDM_REG_AGG_INT_MODE_1 0xc41bc 4170 #define USDM_REG_AGG_INT_MODE_10 0xc41e0 4171 #define USDM_REG_AGG_INT_MODE_11 0xc41e4 4172 #define USDM_REG_AGG_INT_MODE_12 0xc41e8 4173 #define USDM_REG_AGG_INT_MODE_13 0xc41ec 4174 #define USDM_REG_AGG_INT_MODE_14 0xc41f0 4175 #define USDM_REG_AGG_INT_MODE_15 0xc41f4 4176 #define USDM_REG_AGG_INT_MODE_16 0xc41f8 4177 #define USDM_REG_AGG_INT_MODE_17 0xc41fc 4178 #define USDM_REG_AGG_INT_MODE_18 0xc4200 4179 #define USDM_REG_AGG_INT_MODE_19 0xc4204 4180 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4181 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008 4182 /* [RW 16] The maximum value of the competion counter #0 */ 4183 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c 4184 /* [RW 16] The maximum value of the competion counter #1 */ 4185 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020 4186 /* [RW 16] The maximum value of the competion counter #2 */ 4187 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024 4188 /* [RW 16] The maximum value of the competion counter #3 */ 4189 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028 4190 /* [RW 13] The start address in the internal RAM for the completion 4191 counters. */ 4192 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 4193 #define USDM_REG_ENABLE_IN1 0xc4238 4194 #define USDM_REG_ENABLE_IN2 0xc423c 4195 #define USDM_REG_ENABLE_OUT1 0xc4240 4196 #define USDM_REG_ENABLE_OUT2 0xc4244 4197 /* [RW 4] The initial number of messages that can be sent to the pxp control 4198 interface without receiving any ACK. */ 4199 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 4200 /* [ST 32] The number of ACK after placement messages received */ 4201 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 4202 /* [ST 32] The number of packet end messages received from the parser */ 4203 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 4204 /* [ST 32] The number of requests received from the pxp async if */ 4205 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 4206 /* [ST 32] The number of commands received in queue 0 */ 4207 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248 4208 /* [ST 32] The number of commands received in queue 10 */ 4209 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270 4210 /* [ST 32] The number of commands received in queue 11 */ 4211 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274 4212 /* [ST 32] The number of commands received in queue 1 */ 4213 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c 4214 /* [ST 32] The number of commands received in queue 2 */ 4215 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250 4216 /* [ST 32] The number of commands received in queue 3 */ 4217 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254 4218 /* [ST 32] The number of commands received in queue 4 */ 4219 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258 4220 /* [ST 32] The number of commands received in queue 5 */ 4221 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c 4222 /* [ST 32] The number of commands received in queue 6 */ 4223 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260 4224 /* [ST 32] The number of commands received in queue 7 */ 4225 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264 4226 /* [ST 32] The number of commands received in queue 8 */ 4227 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268 4228 /* [ST 32] The number of commands received in queue 9 */ 4229 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c 4230 /* [RW 13] The start address in the internal RAM for the packet end message */ 4231 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 4232 /* [RW 13] The start address in the internal RAM for queue counters */ 4233 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 4234 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4235 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 4236 /* [R 1] parser fifo empty in sdm_sync block */ 4237 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 4238 /* [R 1] parser serial fifo empty in sdm_sync block */ 4239 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 4240 /* [RW 32] Tick for timer counter. Applicable only when 4241 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4242 #define USDM_REG_TIMER_TICK 0xc4000 4243 /* [RW 32] Interrupt mask register #0 read/write */ 4244 #define USDM_REG_USDM_INT_MASK_0 0xc42a0 4245 #define USDM_REG_USDM_INT_MASK_1 0xc42b0 4246 /* [R 32] Interrupt register #0 read */ 4247 #define USDM_REG_USDM_INT_STS_0 0xc4294 4248 #define USDM_REG_USDM_INT_STS_1 0xc42a4 4249 /* [RW 11] Parity mask register #0 read/write */ 4250 #define USDM_REG_USDM_PRTY_MASK 0xc42c0 4251 /* [R 11] Parity register #0 read */ 4252 #define USDM_REG_USDM_PRTY_STS 0xc42b4 4253 /* [RW 5] The number of time_slots in the arbitration cycle */ 4254 #define USEM_REG_ARB_CYCLE_SIZE 0x300034 4255 /* [RW 3] The source that is associated with arbitration element 0. Source 4256 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4257 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4258 #define USEM_REG_ARB_ELEMENT0 0x300020 4259 /* [RW 3] The source that is associated with arbitration element 1. Source 4260 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4261 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4262 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 4263 #define USEM_REG_ARB_ELEMENT1 0x300024 4264 /* [RW 3] The source that is associated with arbitration element 2. Source 4265 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4266 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4267 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4268 and ~usem_registers_arb_element1.arb_element1 */ 4269 #define USEM_REG_ARB_ELEMENT2 0x300028 4270 /* [RW 3] The source that is associated with arbitration element 3. Source 4271 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4272 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4273 not be equal to register ~usem_registers_arb_element0.arb_element0 and 4274 ~usem_registers_arb_element1.arb_element1 and 4275 ~usem_registers_arb_element2.arb_element2 */ 4276 #define USEM_REG_ARB_ELEMENT3 0x30002c 4277 /* [RW 3] The source that is associated with arbitration element 4. Source 4278 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4279 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4280 Could not be equal to register ~usem_registers_arb_element0.arb_element0 4281 and ~usem_registers_arb_element1.arb_element1 and 4282 ~usem_registers_arb_element2.arb_element2 and 4283 ~usem_registers_arb_element3.arb_element3 */ 4284 #define USEM_REG_ARB_ELEMENT4 0x300030 4285 #define USEM_REG_ENABLE_IN 0x3000a4 4286 #define USEM_REG_ENABLE_OUT 0x3000a8 4287 /* [RW 32] This address space contains all registers and memories that are 4288 placed in SEM_FAST block. The SEM_FAST registers are described in 4289 appendix B. In order to access the sem_fast registers the base address 4290 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4291 #define USEM_REG_FAST_MEMORY 0x320000 4292 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4293 by the microcode */ 4294 #define USEM_REG_FIC0_DISABLE 0x300224 4295 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4296 by the microcode */ 4297 #define USEM_REG_FIC1_DISABLE 0x300234 4298 /* [RW 15] Interrupt table Read and write access to it is not possible in 4299 the middle of the work */ 4300 #define USEM_REG_INT_TABLE 0x300400 4301 /* [ST 24] Statistics register. The number of messages that entered through 4302 FIC0 */ 4303 #define USEM_REG_MSG_NUM_FIC0 0x300000 4304 /* [ST 24] Statistics register. The number of messages that entered through 4305 FIC1 */ 4306 #define USEM_REG_MSG_NUM_FIC1 0x300004 4307 /* [ST 24] Statistics register. The number of messages that were sent to 4308 FOC0 */ 4309 #define USEM_REG_MSG_NUM_FOC0 0x300008 4310 /* [ST 24] Statistics register. The number of messages that were sent to 4311 FOC1 */ 4312 #define USEM_REG_MSG_NUM_FOC1 0x30000c 4313 /* [ST 24] Statistics register. The number of messages that were sent to 4314 FOC2 */ 4315 #define USEM_REG_MSG_NUM_FOC2 0x300010 4316 /* [ST 24] Statistics register. The number of messages that were sent to 4317 FOC3 */ 4318 #define USEM_REG_MSG_NUM_FOC3 0x300014 4319 /* [RW 1] Disables input messages from the passive buffer May be updated 4320 during run_time by the microcode */ 4321 #define USEM_REG_PAS_DISABLE 0x30024c 4322 /* [WB 128] Debug only. Passive buffer memory */ 4323 #define USEM_REG_PASSIVE_BUFFER 0x302000 4324 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4325 #define USEM_REG_PRAM 0x340000 4326 /* [R 16] Valid sleeping threads indication have bit per thread */ 4327 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c 4328 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4329 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 4330 /* [RW 16] List of free threads . There is a bit per thread. */ 4331 #define USEM_REG_THREADS_LIST 0x3002e4 4332 /* [RW 3] The arbitration scheme of time_slot 0 */ 4333 #define USEM_REG_TS_0_AS 0x300038 4334 /* [RW 3] The arbitration scheme of time_slot 10 */ 4335 #define USEM_REG_TS_10_AS 0x300060 4336 /* [RW 3] The arbitration scheme of time_slot 11 */ 4337 #define USEM_REG_TS_11_AS 0x300064 4338 /* [RW 3] The arbitration scheme of time_slot 12 */ 4339 #define USEM_REG_TS_12_AS 0x300068 4340 /* [RW 3] The arbitration scheme of time_slot 13 */ 4341 #define USEM_REG_TS_13_AS 0x30006c 4342 /* [RW 3] The arbitration scheme of time_slot 14 */ 4343 #define USEM_REG_TS_14_AS 0x300070 4344 /* [RW 3] The arbitration scheme of time_slot 15 */ 4345 #define USEM_REG_TS_15_AS 0x300074 4346 /* [RW 3] The arbitration scheme of time_slot 16 */ 4347 #define USEM_REG_TS_16_AS 0x300078 4348 /* [RW 3] The arbitration scheme of time_slot 17 */ 4349 #define USEM_REG_TS_17_AS 0x30007c 4350 /* [RW 3] The arbitration scheme of time_slot 18 */ 4351 #define USEM_REG_TS_18_AS 0x300080 4352 /* [RW 3] The arbitration scheme of time_slot 1 */ 4353 #define USEM_REG_TS_1_AS 0x30003c 4354 /* [RW 3] The arbitration scheme of time_slot 2 */ 4355 #define USEM_REG_TS_2_AS 0x300040 4356 /* [RW 3] The arbitration scheme of time_slot 3 */ 4357 #define USEM_REG_TS_3_AS 0x300044 4358 /* [RW 3] The arbitration scheme of time_slot 4 */ 4359 #define USEM_REG_TS_4_AS 0x300048 4360 /* [RW 3] The arbitration scheme of time_slot 5 */ 4361 #define USEM_REG_TS_5_AS 0x30004c 4362 /* [RW 3] The arbitration scheme of time_slot 6 */ 4363 #define USEM_REG_TS_6_AS 0x300050 4364 /* [RW 3] The arbitration scheme of time_slot 7 */ 4365 #define USEM_REG_TS_7_AS 0x300054 4366 /* [RW 3] The arbitration scheme of time_slot 8 */ 4367 #define USEM_REG_TS_8_AS 0x300058 4368 /* [RW 3] The arbitration scheme of time_slot 9 */ 4369 #define USEM_REG_TS_9_AS 0x30005c 4370 /* [RW 32] Interrupt mask register #0 read/write */ 4371 #define USEM_REG_USEM_INT_MASK_0 0x300110 4372 #define USEM_REG_USEM_INT_MASK_1 0x300120 4373 /* [R 32] Interrupt register #0 read */ 4374 #define USEM_REG_USEM_INT_STS_0 0x300104 4375 #define USEM_REG_USEM_INT_STS_1 0x300114 4376 /* [RW 32] Parity mask register #0 read/write */ 4377 #define USEM_REG_USEM_PRTY_MASK_0 0x300130 4378 #define USEM_REG_USEM_PRTY_MASK_1 0x300140 4379 /* [R 32] Parity register #0 read */ 4380 #define USEM_REG_USEM_PRTY_STS_0 0x300124 4381 #define USEM_REG_USEM_PRTY_STS_1 0x300134 4382 /* [RW 2] The queue index for registration on Aux1 counter flag. */ 4383 #define XCM_REG_AUX1_Q 0x20134 4384 /* [RW 2] Per each decision rule the queue index to register to. */ 4385 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 4386 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 4387 #define XCM_REG_CAM_OCCUP 0x20244 4388 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4389 disregarded; valid output is deasserted; all other signals are treated as 4390 usual; if 1 - normal activity. */ 4391 #define XCM_REG_CDU_AG_RD_IFEN 0x20044 4392 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4393 are disregarded; all other signals are treated as usual; if 1 - normal 4394 activity. */ 4395 #define XCM_REG_CDU_AG_WR_IFEN 0x20040 4396 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4397 disregarded; valid output is deasserted; all other signals are treated as 4398 usual; if 1 - normal activity. */ 4399 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c 4400 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4401 input is disregarded; all other signals are treated as usual; if 1 - 4402 normal activity. */ 4403 #define XCM_REG_CDU_SM_WR_IFEN 0x20048 4404 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4405 the initial credit value; read returns the current value of the credit 4406 counter. Must be initialized to 1 at start-up. */ 4407 #define XCM_REG_CFC_INIT_CRD 0x20404 4408 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4409 weight 8 (the most prioritised); 1 stands for weight 1(least 4410 prioritised); 2 stands for weight 2; tc. */ 4411 #define XCM_REG_CP_WEIGHT 0x200dc 4412 /* [RW 1] Input csem Interface enable. If 0 - the valid input is 4413 disregarded; acknowledge output is deasserted; all other signals are 4414 treated as usual; if 1 - normal activity. */ 4415 #define XCM_REG_CSEM_IFEN 0x20028 4416 /* [RC 1] Set at message length mismatch (relative to last indication) at 4417 the csem interface. */ 4418 #define XCM_REG_CSEM_LENGTH_MIS 0x20228 4419 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4420 weight 8 (the most prioritised); 1 stands for weight 1(least 4421 prioritised); 2 stands for weight 2; tc. */ 4422 #define XCM_REG_CSEM_WEIGHT 0x200c4 4423 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4424 disregarded; acknowledge output is deasserted; all other signals are 4425 treated as usual; if 1 - normal activity. */ 4426 #define XCM_REG_DORQ_IFEN 0x20030 4427 /* [RC 1] Set at message length mismatch (relative to last indication) at 4428 the dorq interface. */ 4429 #define XCM_REG_DORQ_LENGTH_MIS 0x20230 4430 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 4431 #define XCM_REG_ERR_EVNT_ID 0x200b0 4432 /* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4433 #define XCM_REG_ERR_XCM_HDR 0x200ac 4434 /* [RW 8] The Event ID for Timers expiration. */ 4435 #define XCM_REG_EXPR_EVNT_ID 0x200b4 4436 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4437 writes the initial credit value; read returns the current value of the 4438 credit counter. Must be initialized to 64 at start-up. */ 4439 #define XCM_REG_FIC0_INIT_CRD 0x2040c 4440 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4441 writes the initial credit value; read returns the current value of the 4442 credit counter. Must be initialized to 64 at start-up. */ 4443 #define XCM_REG_FIC1_INIT_CRD 0x20410 4444 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 4445 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 4446 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 4447 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 4448 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 4449 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 4450 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 4451 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4452 #define XCM_REG_GR_ARB_TYPE 0x2020c 4453 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4454 highest priority is 3. It is supposed that the Channel group is the 4455 compliment of the other 3 groups. */ 4456 #define XCM_REG_GR_LD0_PR 0x20214 4457 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4458 highest priority is 3. It is supposed that the Channel group is the 4459 compliment of the other 3 groups. */ 4460 #define XCM_REG_GR_LD1_PR 0x20218 4461 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 4462 disregarded; acknowledge output is deasserted; all other signals are 4463 treated as usual; if 1 - normal activity. */ 4464 #define XCM_REG_NIG0_IFEN 0x20038 4465 /* [RC 1] Set at message length mismatch (relative to last indication) at 4466 the nig0 interface. */ 4467 #define XCM_REG_NIG0_LENGTH_MIS 0x20238 4468 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 4469 disregarded; acknowledge output is deasserted; all other signals are 4470 treated as usual; if 1 - normal activity. */ 4471 #define XCM_REG_NIG1_IFEN 0x2003c 4472 /* [RC 1] Set at message length mismatch (relative to last indication) at 4473 the nig1 interface. */ 4474 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c 4475 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for 4476 weight 8 (the most prioritised); 1 stands for weight 1(least 4477 prioritised); 2 stands for weight 2; tc. */ 4478 #define XCM_REG_NIG1_WEIGHT 0x200d8 4479 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and 4480 sent to STORM; for a specific connection type. The double REG-pairs are 4481 used in order to align to STORM context row size of 128 bits. The offset 4482 of these data in the STORM context is always 0. Index _i stands for the 4483 connection type (one of 16). */ 4484 #define XCM_REG_N_SM_CTX_LD_0 0x20060 4485 #define XCM_REG_N_SM_CTX_LD_1 0x20064 4486 #define XCM_REG_N_SM_CTX_LD_10 0x20088 4487 #define XCM_REG_N_SM_CTX_LD_11 0x2008c 4488 #define XCM_REG_N_SM_CTX_LD_12 0x20090 4489 #define XCM_REG_N_SM_CTX_LD_13 0x20094 4490 #define XCM_REG_N_SM_CTX_LD_14 0x20098 4491 #define XCM_REG_N_SM_CTX_LD_15 0x2009c 4492 #define XCM_REG_N_SM_CTX_LD_2 0x20068 4493 #define XCM_REG_N_SM_CTX_LD_3 0x2006c 4494 #define XCM_REG_N_SM_CTX_LD_4 0x20070 4495 #define XCM_REG_N_SM_CTX_LD_5 0x20074 4496 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4497 acknowledge output is deasserted; all other signals are treated as usual; 4498 if 1 - normal activity. */ 4499 #define XCM_REG_PBF_IFEN 0x20034 4500 /* [RC 1] Set at message length mismatch (relative to last indication) at 4501 the pbf interface. */ 4502 #define XCM_REG_PBF_LENGTH_MIS 0x20234 4503 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4504 weight 8 (the most prioritised); 1 stands for weight 1(least 4505 prioritised); 2 stands for weight 2; tc. */ 4506 #define XCM_REG_PBF_WEIGHT 0x200d0 4507 #define XCM_REG_PHYS_QNUM3_0 0x20100 4508 #define XCM_REG_PHYS_QNUM3_1 0x20104 4509 /* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4510 #define XCM_REG_STOP_EVNT_ID 0x200b8 4511 /* [RC 1] Set at message length mismatch (relative to last indication) at 4512 the STORM interface. */ 4513 #define XCM_REG_STORM_LENGTH_MIS 0x2021c 4514 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4515 weight 8 (the most prioritised); 1 stands for weight 1(least 4516 prioritised); 2 stands for weight 2; tc. */ 4517 #define XCM_REG_STORM_WEIGHT 0x200bc 4518 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4519 disregarded; acknowledge output is deasserted; all other signals are 4520 treated as usual; if 1 - normal activity. */ 4521 #define XCM_REG_STORM_XCM_IFEN 0x20010 4522 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4523 writes the initial credit value; read returns the current value of the 4524 credit counter. Must be initialized to 4 at start-up. */ 4525 #define XCM_REG_TM_INIT_CRD 0x2041c 4526 /* [RW 28] The CM header for Timers expiration command. */ 4527 #define XCM_REG_TM_XCM_HDR 0x200a8 4528 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4529 disregarded; acknowledge output is deasserted; all other signals are 4530 treated as usual; if 1 - normal activity. */ 4531 #define XCM_REG_TM_XCM_IFEN 0x2001c 4532 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is 4533 disregarded; acknowledge output is deasserted; all other signals are 4534 treated as usual; if 1 - normal activity. */ 4535 #define XCM_REG_TSEM_IFEN 0x20024 4536 /* [RC 1] Set at message length mismatch (relative to last indication) at 4537 the tsem interface. */ 4538 #define XCM_REG_TSEM_LENGTH_MIS 0x20224 4539 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 4540 weight 8 (the most prioritised); 1 stands for weight 1(least 4541 prioritised); 2 stands for weight 2; tc. */ 4542 #define XCM_REG_TSEM_WEIGHT 0x200c0 4543 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 4544 #define XCM_REG_UNA_GT_NXT_Q 0x20120 4545 /* [RW 1] Input usem Interface enable. If 0 - the valid input is 4546 disregarded; acknowledge output is deasserted; all other signals are 4547 treated as usual; if 1 - normal activity. */ 4548 #define XCM_REG_USEM_IFEN 0x2002c 4549 /* [RC 1] Message length mismatch (relative to last indication) at the usem 4550 interface. */ 4551 #define XCM_REG_USEM_LENGTH_MIS 0x2022c 4552 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4553 weight 8 (the most prioritised); 1 stands for weight 1(least 4554 prioritised); 2 stands for weight 2; tc. */ 4555 #define XCM_REG_USEM_WEIGHT 0x200c8 4556 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 4557 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8 4558 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc 4559 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0 4560 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 4561 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 4562 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 4563 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 4564 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 4565 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 4566 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 4567 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 4568 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4569 acknowledge output is deasserted; all other signals are treated as usual; 4570 if 1 - normal activity. */ 4571 #define XCM_REG_XCM_CFC_IFEN 0x20050 4572 /* [RW 14] Interrupt mask register #0 read/write */ 4573 #define XCM_REG_XCM_INT_MASK 0x202b4 4574 /* [R 14] Interrupt register #0 read */ 4575 #define XCM_REG_XCM_INT_STS 0x202a8 4576 /* [R 30] Parity register #0 read */ 4577 #define XCM_REG_XCM_PRTY_STS 0x202b8 4578 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 4579 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4580 Is used to determine the number of the AG context REG-pairs written back; 4581 when the Reg1WbFlg isn't set. */ 4582 #define XCM_REG_XCM_REG0_SZ 0x200f4 4583 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4584 disregarded; valid is deasserted; all other signals are treated as usual; 4585 if 1 - normal activity. */ 4586 #define XCM_REG_XCM_STORM0_IFEN 0x20004 4587 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4588 disregarded; valid is deasserted; all other signals are treated as usual; 4589 if 1 - normal activity. */ 4590 #define XCM_REG_XCM_STORM1_IFEN 0x20008 4591 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 4592 disregarded; acknowledge output is deasserted; all other signals are 4593 treated as usual; if 1 - normal activity. */ 4594 #define XCM_REG_XCM_TM_IFEN 0x20020 4595 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4596 disregarded; valid is deasserted; all other signals are treated as usual; 4597 if 1 - normal activity. */ 4598 #define XCM_REG_XCM_XQM_IFEN 0x2000c 4599 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4600 #define XCM_REG_XCM_XQM_USE_Q 0x200f0 4601 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 4602 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 4603 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4604 the initial credit value; read returns the current value of the credit 4605 counter. Must be initialized to 32 at start-up. */ 4606 #define XCM_REG_XQM_INIT_CRD 0x20420 4607 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4608 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4609 prioritised); 2 stands for weight 2; tc. */ 4610 #define XCM_REG_XQM_P_WEIGHT 0x200e4 4611 /* [RW 28] The CM header value for QM request (primary). */ 4612 #define XCM_REG_XQM_XCM_HDR_P 0x200a0 4613 /* [RW 28] The CM header value for QM request (secondary). */ 4614 #define XCM_REG_XQM_XCM_HDR_S 0x200a4 4615 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4616 acknowledge output is deasserted; all other signals are treated as usual; 4617 if 1 - normal activity. */ 4618 #define XCM_REG_XQM_XCM_IFEN 0x20014 4619 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4620 acknowledge output is deasserted; all other signals are treated as usual; 4621 if 1 - normal activity. */ 4622 #define XCM_REG_XSDM_IFEN 0x20018 4623 /* [RC 1] Set at message length mismatch (relative to last indication) at 4624 the SDM interface. */ 4625 #define XCM_REG_XSDM_LENGTH_MIS 0x20220 4626 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4627 weight 8 (the most prioritised); 1 stands for weight 1(least 4628 prioritised); 2 stands for weight 2; tc. */ 4629 #define XCM_REG_XSDM_WEIGHT 0x200e0 4630 /* [RW 17] Indirect access to the descriptor table of the XX protection 4631 mechanism. The fields are: [5:0] - message length; 11:6] - message 4632 pointer; 16:12] - next pointer. */ 4633 #define XCM_REG_XX_DESCR_TABLE 0x20480 4634 #define XCM_REG_XX_DESCR_TABLE_SIZE 32 4635 /* [R 6] Used to read the XX protection Free counter. */ 4636 #define XCM_REG_XX_FREE 0x20240 4637 /* [RW 6] Initial value for the credit counter; responsible for fulfilling 4638 of the Input Stage XX protection buffer by the XX protection pending 4639 messages. Max credit available - 3.Write writes the initial credit value; 4640 read returns the current value of the credit counter. Must be initialized 4641 to 2 at start-up. */ 4642 #define XCM_REG_XX_INIT_CRD 0x20424 4643 /* [RW 6] The maximum number of pending messages; which may be stored in XX 4644 protection. ~xcm_registers_xx_free.xx_free read on read. */ 4645 #define XCM_REG_XX_MSG_NUM 0x20428 4646 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4647 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 4648 /* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4649 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 4650 header pointer. */ 4651 #define XCM_REG_XX_TABLE 0x20500 4652 /* [RW 8] The event id for aggregated interrupt 0 */ 4653 #define XSDM_REG_AGG_INT_EVENT_0 0x166038 4654 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c 4655 #define XSDM_REG_AGG_INT_EVENT_10 0x166060 4656 #define XSDM_REG_AGG_INT_EVENT_11 0x166064 4657 #define XSDM_REG_AGG_INT_EVENT_12 0x166068 4658 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c 4659 #define XSDM_REG_AGG_INT_EVENT_14 0x166070 4660 #define XSDM_REG_AGG_INT_EVENT_15 0x166074 4661 #define XSDM_REG_AGG_INT_EVENT_16 0x166078 4662 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c 4663 #define XSDM_REG_AGG_INT_EVENT_18 0x166080 4664 #define XSDM_REG_AGG_INT_EVENT_19 0x166084 4665 #define XSDM_REG_AGG_INT_EVENT_10 0x166060 4666 #define XSDM_REG_AGG_INT_EVENT_11 0x166064 4667 #define XSDM_REG_AGG_INT_EVENT_12 0x166068 4668 #define XSDM_REG_AGG_INT_EVENT_2 0x166040 4669 #define XSDM_REG_AGG_INT_EVENT_20 0x166088 4670 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c 4671 #define XSDM_REG_AGG_INT_EVENT_22 0x166090 4672 #define XSDM_REG_AGG_INT_EVENT_23 0x166094 4673 #define XSDM_REG_AGG_INT_EVENT_24 0x166098 4674 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c 4675 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0 4676 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4 4677 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8 4678 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac 4679 #define XSDM_REG_AGG_INT_EVENT_3 0x166044 4680 #define XSDM_REG_AGG_INT_EVENT_30 0x1660b0 4681 #define XSDM_REG_AGG_INT_EVENT_31 0x1660b4 4682 #define XSDM_REG_AGG_INT_EVENT_4 0x166048 4683 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c 4684 #define XSDM_REG_AGG_INT_EVENT_6 0x166050 4685 #define XSDM_REG_AGG_INT_EVENT_7 0x166054 4686 #define XSDM_REG_AGG_INT_EVENT_8 0x166058 4687 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c 4688 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4689 or auto-mask-mode (1) */ 4690 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8 4691 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc 4692 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0 4693 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4 4694 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8 4695 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec 4696 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0 4697 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4 4698 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8 4699 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc 4700 #define XSDM_REG_AGG_INT_MODE_18 0x166200 4701 #define XSDM_REG_AGG_INT_MODE_19 0x166204 4702 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4703 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008 4704 /* [RW 16] The maximum value of the competion counter #0 */ 4705 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 4706 /* [RW 16] The maximum value of the competion counter #1 */ 4707 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020 4708 /* [RW 16] The maximum value of the competion counter #2 */ 4709 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024 4710 /* [RW 16] The maximum value of the competion counter #3 */ 4711 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028 4712 /* [RW 13] The start address in the internal RAM for the completion 4713 counters. */ 4714 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 4715 #define XSDM_REG_ENABLE_IN1 0x166238 4716 #define XSDM_REG_ENABLE_IN2 0x16623c 4717 #define XSDM_REG_ENABLE_OUT1 0x166240 4718 #define XSDM_REG_ENABLE_OUT2 0x166244 4719 /* [RW 4] The initial number of messages that can be sent to the pxp control 4720 interface without receiving any ACK. */ 4721 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 4722 /* [ST 32] The number of ACK after placement messages received */ 4723 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 4724 /* [ST 32] The number of packet end messages received from the parser */ 4725 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 4726 /* [ST 32] The number of requests received from the pxp async if */ 4727 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 4728 /* [ST 32] The number of commands received in queue 0 */ 4729 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248 4730 /* [ST 32] The number of commands received in queue 10 */ 4731 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 4732 /* [ST 32] The number of commands received in queue 11 */ 4733 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270 4734 /* [ST 32] The number of commands received in queue 1 */ 4735 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 4736 /* [ST 32] The number of commands received in queue 3 */ 4737 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250 4738 /* [ST 32] The number of commands received in queue 4 */ 4739 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254 4740 /* [ST 32] The number of commands received in queue 5 */ 4741 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258 4742 /* [ST 32] The number of commands received in queue 6 */ 4743 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 4744 /* [ST 32] The number of commands received in queue 7 */ 4745 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260 4746 /* [ST 32] The number of commands received in queue 8 */ 4747 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264 4748 /* [ST 32] The number of commands received in queue 9 */ 4749 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268 4750 /* [RW 13] The start address in the internal RAM for queue counters */ 4751 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 4752 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4753 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 4754 /* [R 1] parser fifo empty in sdm_sync block */ 4755 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 4756 /* [R 1] parser serial fifo empty in sdm_sync block */ 4757 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 4758 /* [RW 32] Tick for timer counter. Applicable only when 4759 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4760 #define XSDM_REG_TIMER_TICK 0x166000 4761 /* [RW 32] Interrupt mask register #0 read/write */ 4762 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c 4763 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 4764 /* [R 32] Interrupt register #0 read */ 4765 #define XSDM_REG_XSDM_INT_STS_0 0x166290 4766 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 4767 /* [RW 11] Parity mask register #0 read/write */ 4768 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 4769 /* [R 11] Parity register #0 read */ 4770 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 4771 /* [RW 5] The number of time_slots in the arbitration cycle */ 4772 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 4773 /* [RW 3] The source that is associated with arbitration element 0. Source 4774 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4775 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4776 #define XSEM_REG_ARB_ELEMENT0 0x280020 4777 /* [RW 3] The source that is associated with arbitration element 1. Source 4778 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4779 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4780 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 4781 #define XSEM_REG_ARB_ELEMENT1 0x280024 4782 /* [RW 3] The source that is associated with arbitration element 2. Source 4783 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4784 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4785 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 4786 and ~xsem_registers_arb_element1.arb_element1 */ 4787 #define XSEM_REG_ARB_ELEMENT2 0x280028 4788 /* [RW 3] The source that is associated with arbitration element 3. Source 4789 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4790 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4791 not be equal to register ~xsem_registers_arb_element0.arb_element0 and 4792 ~xsem_registers_arb_element1.arb_element1 and 4793 ~xsem_registers_arb_element2.arb_element2 */ 4794 #define XSEM_REG_ARB_ELEMENT3 0x28002c 4795 /* [RW 3] The source that is associated with arbitration element 4. Source 4796 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4797 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4798 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 4799 and ~xsem_registers_arb_element1.arb_element1 and 4800 ~xsem_registers_arb_element2.arb_element2 and 4801 ~xsem_registers_arb_element3.arb_element3 */ 4802 #define XSEM_REG_ARB_ELEMENT4 0x280030 4803 #define XSEM_REG_ENABLE_IN 0x2800a4 4804 #define XSEM_REG_ENABLE_OUT 0x2800a8 4805 /* [RW 32] This address space contains all registers and memories that are 4806 placed in SEM_FAST block. The SEM_FAST registers are described in 4807 appendix B. In order to access the sem_fast registers the base address 4808 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4809 #define XSEM_REG_FAST_MEMORY 0x2a0000 4810 /* [RW 1] Disables input messages from FIC0 May be updated during run_time 4811 by the microcode */ 4812 #define XSEM_REG_FIC0_DISABLE 0x280224 4813 /* [RW 1] Disables input messages from FIC1 May be updated during run_time 4814 by the microcode */ 4815 #define XSEM_REG_FIC1_DISABLE 0x280234 4816 /* [RW 15] Interrupt table Read and write access to it is not possible in 4817 the middle of the work */ 4818 #define XSEM_REG_INT_TABLE 0x280400 4819 /* [ST 24] Statistics register. The number of messages that entered through 4820 FIC0 */ 4821 #define XSEM_REG_MSG_NUM_FIC0 0x280000 4822 /* [ST 24] Statistics register. The number of messages that entered through 4823 FIC1 */ 4824 #define XSEM_REG_MSG_NUM_FIC1 0x280004 4825 /* [ST 24] Statistics register. The number of messages that were sent to 4826 FOC0 */ 4827 #define XSEM_REG_MSG_NUM_FOC0 0x280008 4828 /* [ST 24] Statistics register. The number of messages that were sent to 4829 FOC1 */ 4830 #define XSEM_REG_MSG_NUM_FOC1 0x28000c 4831 /* [ST 24] Statistics register. The number of messages that were sent to 4832 FOC2 */ 4833 #define XSEM_REG_MSG_NUM_FOC2 0x280010 4834 /* [ST 24] Statistics register. The number of messages that were sent to 4835 FOC3 */ 4836 #define XSEM_REG_MSG_NUM_FOC3 0x280014 4837 /* [RW 1] Disables input messages from the passive buffer May be updated 4838 during run_time by the microcode */ 4839 #define XSEM_REG_PAS_DISABLE 0x28024c 4840 /* [WB 128] Debug only. Passive buffer memory */ 4841 #define XSEM_REG_PASSIVE_BUFFER 0x282000 4842 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4843 #define XSEM_REG_PRAM 0x2c0000 4844 /* [R 16] Valid sleeping threads indication have bit per thread */ 4845 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 4846 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4847 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 4848 /* [RW 16] List of free threads . There is a bit per thread. */ 4849 #define XSEM_REG_THREADS_LIST 0x2802e4 4850 /* [RW 3] The arbitration scheme of time_slot 0 */ 4851 #define XSEM_REG_TS_0_AS 0x280038 4852 /* [RW 3] The arbitration scheme of time_slot 10 */ 4853 #define XSEM_REG_TS_10_AS 0x280060 4854 /* [RW 3] The arbitration scheme of time_slot 11 */ 4855 #define XSEM_REG_TS_11_AS 0x280064 4856 /* [RW 3] The arbitration scheme of time_slot 12 */ 4857 #define XSEM_REG_TS_12_AS 0x280068 4858 /* [RW 3] The arbitration scheme of time_slot 13 */ 4859 #define XSEM_REG_TS_13_AS 0x28006c 4860 /* [RW 3] The arbitration scheme of time_slot 14 */ 4861 #define XSEM_REG_TS_14_AS 0x280070 4862 /* [RW 3] The arbitration scheme of time_slot 15 */ 4863 #define XSEM_REG_TS_15_AS 0x280074 4864 /* [RW 3] The arbitration scheme of time_slot 16 */ 4865 #define XSEM_REG_TS_16_AS 0x280078 4866 /* [RW 3] The arbitration scheme of time_slot 17 */ 4867 #define XSEM_REG_TS_17_AS 0x28007c 4868 /* [RW 3] The arbitration scheme of time_slot 18 */ 4869 #define XSEM_REG_TS_18_AS 0x280080 4870 /* [RW 3] The arbitration scheme of time_slot 1 */ 4871 #define XSEM_REG_TS_1_AS 0x28003c 4872 /* [RW 3] The arbitration scheme of time_slot 2 */ 4873 #define XSEM_REG_TS_2_AS 0x280040 4874 /* [RW 3] The arbitration scheme of time_slot 3 */ 4875 #define XSEM_REG_TS_3_AS 0x280044 4876 /* [RW 3] The arbitration scheme of time_slot 4 */ 4877 #define XSEM_REG_TS_4_AS 0x280048 4878 /* [RW 3] The arbitration scheme of time_slot 5 */ 4879 #define XSEM_REG_TS_5_AS 0x28004c 4880 /* [RW 3] The arbitration scheme of time_slot 6 */ 4881 #define XSEM_REG_TS_6_AS 0x280050 4882 /* [RW 3] The arbitration scheme of time_slot 7 */ 4883 #define XSEM_REG_TS_7_AS 0x280054 4884 /* [RW 3] The arbitration scheme of time_slot 8 */ 4885 #define XSEM_REG_TS_8_AS 0x280058 4886 /* [RW 3] The arbitration scheme of time_slot 9 */ 4887 #define XSEM_REG_TS_9_AS 0x28005c 4888 /* [RW 32] Interrupt mask register #0 read/write */ 4889 #define XSEM_REG_XSEM_INT_MASK_0 0x280110 4890 #define XSEM_REG_XSEM_INT_MASK_1 0x280120 4891 /* [R 32] Interrupt register #0 read */ 4892 #define XSEM_REG_XSEM_INT_STS_0 0x280104 4893 #define XSEM_REG_XSEM_INT_STS_1 0x280114 4894 /* [RW 32] Parity mask register #0 read/write */ 4895 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 4896 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 4897 /* [R 32] Parity register #0 read */ 4898 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 4899 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 4900 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 4901 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 4902 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 4903 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 4904 #define MCPR_NVM_COMMAND_DOIT (1L<<4) 4905 #define MCPR_NVM_COMMAND_DONE (1L<<3) 4906 #define MCPR_NVM_COMMAND_FIRST (1L<<7) 4907 #define MCPR_NVM_COMMAND_LAST (1L<<8) 4908 #define MCPR_NVM_COMMAND_WR (1L<<5) 4909 #define MCPR_NVM_COMMAND_WREN (1L<<16) 4910 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16 4911 #define MCPR_NVM_COMMAND_WRDI (1L<<17) 4912 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17 4913 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 4914 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 4915 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 4916 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 4917 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 4918 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 4919 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 4920 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 4921 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 4922 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 4923 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 4924 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 4925 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 4926 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 4927 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 4928 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 4929 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 4930 #define EMAC_LED_1000MB_OVERRIDE (1L<<1) 4931 #define EMAC_LED_100MB_OVERRIDE (1L<<2) 4932 #define EMAC_LED_10MB_OVERRIDE (1L<<3) 4933 #define EMAC_LED_2500MB_OVERRIDE (1L<<12) 4934 #define EMAC_LED_OVERRIDE (1L<<0) 4935 #define EMAC_LED_TRAFFIC (1L<<6) 4936 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 4937 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 4938 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 4939 #define EMAC_MDIO_COMM_DATA (0xffffL<<0) 4940 #define EMAC_MDIO_COMM_START_BUSY (1L<<29) 4941 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 4942 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 4943 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) 4944 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 4945 #define EMAC_MODE_25G_MODE (1L<<5) 4946 #define EMAC_MODE_HALF_DUPLEX (1L<<1) 4947 #define EMAC_MODE_PORT_GMII (2L<<2) 4948 #define EMAC_MODE_PORT_MII (1L<<2) 4949 #define EMAC_MODE_PORT_MII_10M (3L<<2) 4950 #define EMAC_MODE_RESET (1L<<0) 4951 #define EMAC_REG_EMAC_LED 0xc 4952 #define EMAC_REG_EMAC_MAC_MATCH 0x10 4953 #define EMAC_REG_EMAC_MDIO_COMM 0xac 4954 #define EMAC_REG_EMAC_MDIO_MODE 0xb4 4955 #define EMAC_REG_EMAC_MODE 0x0 4956 #define EMAC_REG_EMAC_RX_MODE 0xc8 4957 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 4958 #define EMAC_REG_EMAC_RX_STAT_AC 0x180 4959 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 4960 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 4961 #define EMAC_REG_EMAC_TX_MODE 0xbc 4962 #define EMAC_REG_EMAC_TX_STAT_AC 0x280 4963 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 4964 #define EMAC_RX_MODE_FLOW_EN (1L<<2) 4965 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 4966 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 4967 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 4968 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 4969 #define EMAC_TX_MODE_FLOW_EN (1L<<4) 4970 #define MISC_REGISTERS_GPIO_0 0 4971 #define MISC_REGISTERS_GPIO_1 1 4972 #define MISC_REGISTERS_GPIO_2 2 4973 #define MISC_REGISTERS_GPIO_3 3 4974 #define MISC_REGISTERS_GPIO_CLR_POS 16 4975 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 4976 #define MISC_REGISTERS_GPIO_FLOAT_POS 24 4977 #define MISC_REGISTERS_GPIO_HIGH 1 4978 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 4979 #define MISC_REGISTERS_GPIO_LOW 0 4980 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 4981 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 4982 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4983 #define MISC_REGISTERS_GPIO_SET_POS 8 4984 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 4985 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 4986 #define MISC_REGISTERS_RESET_REG_1_SET 0x584 4987 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 4988 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 4989 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 4990 #define MISC_REGISTERS_RESET_REG_2_SET 0x594 4991 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 4992 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 4993 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 4994 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 4995 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 4996 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 4997 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 4998 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 4999 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 5000 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 5001 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 5002 #define MISC_REGISTERS_SPIO_4 4 5003 #define MISC_REGISTERS_SPIO_5 5 5004 #define MISC_REGISTERS_SPIO_7 7 5005 #define MISC_REGISTERS_SPIO_CLR_POS 16 5006 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 5007 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000 5008 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000 5009 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000 5010 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000 5011 #define MISC_REGISTERS_SPIO_FLOAT_POS 24 5012 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 5013 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 5014 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 5015 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 5016 #define MISC_REGISTERS_SPIO_SET_POS 8 5017 #define HW_LOCK_MAX_RESOURCE_VALUE 31 5018 #define HW_LOCK_RESOURCE_8072_MDIO 0 5019 #define HW_LOCK_RESOURCE_GPIO 1 5020 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5021 #define HW_LOCK_RESOURCE_SPIO 2 5022 #define HW_LOCK_RESOURCE_UNDI 5 5023 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5024 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5025 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5026 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8) 5027 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7) 5028 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6) 5029 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29) 5030 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28) 5031 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1) 5032 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0) 5033 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18) 5034 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) 5035 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) 5036 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) 5037 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) 5038 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15) 5039 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14) 5040 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20) 5041 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0) 5042 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31) 5043 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3) 5044 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2) 5045 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5) 5046 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4) 5047 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) 5048 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) 5049 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) 5050 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) 5051 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) 5052 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) 5053 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) 5054 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24) 5055 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29) 5056 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28) 5057 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23) 5058 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27) 5059 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26) 5060 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21) 5061 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20) 5062 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25) 5063 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24) 5064 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16) 5065 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9) 5066 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7) 5067 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6) 5068 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11) 5069 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) 5070 #define RESERVED_GENERAL_ATTENTION_BIT_0 0 5071 5072 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0 5073 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5074 5075 #define RESERVED_GENERAL_ATTENTION_BIT_6 6 5076 #define RESERVED_GENERAL_ATTENTION_BIT_7 7 5077 #define RESERVED_GENERAL_ATTENTION_BIT_8 8 5078 #define RESERVED_GENERAL_ATTENTION_BIT_9 9 5079 #define RESERVED_GENERAL_ATTENTION_BIT_10 10 5080 #define RESERVED_GENERAL_ATTENTION_BIT_11 11 5081 #define RESERVED_GENERAL_ATTENTION_BIT_12 12 5082 #define RESERVED_GENERAL_ATTENTION_BIT_13 13 5083 #define RESERVED_GENERAL_ATTENTION_BIT_14 14 5084 #define RESERVED_GENERAL_ATTENTION_BIT_15 15 5085 #define RESERVED_GENERAL_ATTENTION_BIT_16 16 5086 #define RESERVED_GENERAL_ATTENTION_BIT_17 17 5087 #define RESERVED_GENERAL_ATTENTION_BIT_18 18 5088 #define RESERVED_GENERAL_ATTENTION_BIT_19 19 5089 #define RESERVED_GENERAL_ATTENTION_BIT_20 20 5090 #define RESERVED_GENERAL_ATTENTION_BIT_21 21 5091 5092 /* storm asserts attention bits */ 5093 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 5094 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 5095 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 5096 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 5097 5098 /* mcp error attention bit */ 5099 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5100 5101 /*E1H NIG status sync attention mapped to group 4-7*/ 5102 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 5103 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 5104 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 5105 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 5106 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 5107 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 5108 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 5109 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 5110 5111 5112 #define LATCHED_ATTN_RBCR 23 5113 #define LATCHED_ATTN_RBCT 24 5114 #define LATCHED_ATTN_RBCN 25 5115 #define LATCHED_ATTN_RBCU 26 5116 #define LATCHED_ATTN_RBCP 27 5117 #define LATCHED_ATTN_TIMEOUT_GRC 28 5118 #define LATCHED_ATTN_RSVD_GRC 29 5119 #define LATCHED_ATTN_ROM_PARITY_MCP 30 5120 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 5121 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 5122 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 5123 5124 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 5125 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32)) 5126 /* 5127 * This file defines GRC base address for every block. 5128 * This file is included by chipsim, asm microcode and cpp microcode. 5129 * These values are used in Design.xml on regBase attribute 5130 * Use the base with the generated offsets of specific registers. 5131 */ 5132 5133 #define GRCBASE_PXPCS 0x000000 5134 #define GRCBASE_PCICONFIG 0x002000 5135 #define GRCBASE_PCIREG 0x002400 5136 #define GRCBASE_EMAC0 0x008000 5137 #define GRCBASE_EMAC1 0x008400 5138 #define GRCBASE_DBU 0x008800 5139 #define GRCBASE_MISC 0x00A000 5140 #define GRCBASE_DBG 0x00C000 5141 #define GRCBASE_NIG 0x010000 5142 #define GRCBASE_XCM 0x020000 5143 #define GRCBASE_PRS 0x040000 5144 #define GRCBASE_SRCH 0x040400 5145 #define GRCBASE_TSDM 0x042000 5146 #define GRCBASE_TCM 0x050000 5147 #define GRCBASE_BRB1 0x060000 5148 #define GRCBASE_MCP 0x080000 5149 #define GRCBASE_UPB 0x0C1000 5150 #define GRCBASE_CSDM 0x0C2000 5151 #define GRCBASE_USDM 0x0C4000 5152 #define GRCBASE_CCM 0x0D0000 5153 #define GRCBASE_UCM 0x0E0000 5154 #define GRCBASE_CDU 0x101000 5155 #define GRCBASE_DMAE 0x102000 5156 #define GRCBASE_PXP 0x103000 5157 #define GRCBASE_CFC 0x104000 5158 #define GRCBASE_HC 0x108000 5159 #define GRCBASE_PXP2 0x120000 5160 #define GRCBASE_PBF 0x140000 5161 #define GRCBASE_XPB 0x161000 5162 #define GRCBASE_TIMERS 0x164000 5163 #define GRCBASE_XSDM 0x166000 5164 #define GRCBASE_QM 0x168000 5165 #define GRCBASE_DQ 0x170000 5166 #define GRCBASE_TSEM 0x180000 5167 #define GRCBASE_CSEM 0x200000 5168 #define GRCBASE_XSEM 0x280000 5169 #define GRCBASE_USEM 0x300000 5170 #define GRCBASE_MISC_AEU GRCBASE_MISC 5171 5172 5173 /* offset of configuration space in the pci core register */ 5174 #define PCICFG_OFFSET 0x2000 5175 #define PCICFG_VENDOR_ID_OFFSET 0x00 5176 #define PCICFG_DEVICE_ID_OFFSET 0x02 5177 #define PCICFG_COMMAND_OFFSET 0x04 5178 #define PCICFG_COMMAND_IO_SPACE (1<<0) 5179 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 5180 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 5181 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 5182 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 5183 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 5184 #define PCICFG_COMMAND_PERR_ENA (1<<6) 5185 #define PCICFG_COMMAND_STEPPING (1<<7) 5186 #define PCICFG_COMMAND_SERR_ENA (1<<8) 5187 #define PCICFG_COMMAND_FAST_B2B (1<<9) 5188 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 5189 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 5190 #define PCICFG_STATUS_OFFSET 0x06 5191 #define PCICFG_REVESION_ID 0x08 5192 #define PCICFG_CACHE_LINE_SIZE 0x0c 5193 #define PCICFG_LATENCY_TIMER 0x0d 5194 #define PCICFG_BAR_1_LOW 0x10 5195 #define PCICFG_BAR_1_HIGH 0x14 5196 #define PCICFG_BAR_2_LOW 0x18 5197 #define PCICFG_BAR_2_HIGH 0x1c 5198 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5199 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5200 #define PCICFG_INT_LINE 0x3c 5201 #define PCICFG_INT_PIN 0x3d 5202 #define PCICFG_PM_CAPABILITY 0x48 5203 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 5204 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 5205 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 5206 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 5207 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 5208 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 5209 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 5210 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 5211 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 5212 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 5213 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 5214 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 5215 #define PCICFG_PM_CSR_OFFSET 0x4c 5216 #define PCICFG_PM_CSR_STATE (0x3<<0) 5217 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 5218 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 5219 #define PCICFG_GRC_ADDRESS 0x78 5220 #define PCICFG_GRC_DATA 0x80 5221 #define PCICFG_DEVICE_CONTROL 0xb4 5222 #define PCICFG_LINK_CONTROL 0xbc 5223 5224 5225 #define BAR_USTRORM_INTMEM 0x400000 5226 #define BAR_CSTRORM_INTMEM 0x410000 5227 #define BAR_XSTRORM_INTMEM 0x420000 5228 #define BAR_TSTRORM_INTMEM 0x430000 5229 5230 /* for accessing the IGU in case of status block ACK */ 5231 #define BAR_IGU_INTMEM 0x440000 5232 5233 #define BAR_DOORBELL_OFFSET 0x800000 5234 5235 #define BAR_ME_REGISTER 0x450000 5236 5237 /* config_2 offset */ 5238 #define GRC_CONFIG_2_SIZE_REG 0x408 5239 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 5240 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 5241 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 5242 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 5243 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 5244 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 5245 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 5246 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 5247 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 5248 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 5249 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 5250 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 5251 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 5252 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 5253 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 5254 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 5255 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 5256 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 5257 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 5258 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 5259 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 5260 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 5261 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 5262 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 5263 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 5264 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 5265 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 5266 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 5267 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 5268 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 5269 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 5270 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 5271 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 5272 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 5273 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 5274 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 5275 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 5276 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 5277 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 5278 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 5279 5280 /* config_3 offset */ 5281 #define GRC_CONFIG_3_SIZE_REG 0x40c 5282 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 5283 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 5284 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 5285 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 5286 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 5287 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 5288 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 5289 5290 #define GRC_BAR2_CONFIG 0x4e0 5291 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 5292 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 5293 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 5294 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 5295 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 5296 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 5297 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 5298 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 5299 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 5300 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 5301 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 5302 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 5303 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 5304 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 5305 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 5306 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 5307 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 5308 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 5309 5310 #define PCI_PM_DATA_A 0x410 5311 #define PCI_PM_DATA_B 0x414 5312 #define PCI_ID_VAL1 0x434 5313 #define PCI_ID_VAL2 0x438 5314 5315 5316 #define MDIO_REG_BANK_CL73_IEEEB0 0x0 5317 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 5318 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 5319 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 5320 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 5321 5322 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 5323 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 5324 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 5325 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 5326 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 5327 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 5328 5329 #define MDIO_REG_BANK_RX0 0x80b0 5330 #define MDIO_RX0_RX_EQ_BOOST 0x1c 5331 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5332 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 5333 5334 #define MDIO_REG_BANK_RX1 0x80c0 5335 #define MDIO_RX1_RX_EQ_BOOST 0x1c 5336 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5337 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 5338 5339 #define MDIO_REG_BANK_RX2 0x80d0 5340 #define MDIO_RX2_RX_EQ_BOOST 0x1c 5341 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5342 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 5343 5344 #define MDIO_REG_BANK_RX3 0x80e0 5345 #define MDIO_RX3_RX_EQ_BOOST 0x1c 5346 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5347 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 5348 5349 #define MDIO_REG_BANK_RX_ALL 0x80f0 5350 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 5351 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5352 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 5353 5354 #define MDIO_REG_BANK_TX0 0x8060 5355 #define MDIO_TX0_TX_DRIVER 0x17 5356 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 5357 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 5358 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5359 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 5360 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5361 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 5362 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 5363 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5364 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5365 5366 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 5367 #define MDIO_BLOCK0_XGXS_CONTROL 0x10 5368 5369 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 5370 #define MDIO_BLOCK1_LANE_CTRL0 0x15 5371 #define MDIO_BLOCK1_LANE_CTRL1 0x16 5372 #define MDIO_BLOCK1_LANE_CTRL2 0x17 5373 #define MDIO_BLOCK1_LANE_PRBS 0x19 5374 5375 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 5376 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 5377 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 5378 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 5379 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 5380 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 5381 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 5382 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 5383 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 5384 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 5385 5386 #define MDIO_REG_BANK_GP_STATUS 0x8120 5387 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 5388 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 5389 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 5390 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 5391 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 5392 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 5393 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 5394 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 5395 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 5396 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 5397 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 5398 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 5399 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 5400 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 5401 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 5402 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 5403 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 5404 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 5405 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 5406 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 5407 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 5408 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 5409 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 5410 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 5411 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 5412 5413 5414 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 5415 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 5416 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 5417 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 5418 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 5419 5420 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 5421 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 5422 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 5423 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 5424 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 5425 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 5426 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 5427 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 5428 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 5429 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 5430 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 5431 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 5432 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 5433 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 5434 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 5435 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 5436 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 5437 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 5438 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 5439 #define MDIO_SERDES_DIGITAL_MISC1 0x18 5440 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 5441 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 5442 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 5443 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 5444 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 5445 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 5446 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 5447 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 5448 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 5449 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 5450 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 5451 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 5452 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 5453 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 5454 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 5455 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 5456 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 5457 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 5458 5459 #define MDIO_REG_BANK_OVER_1G 0x8320 5460 #define MDIO_OVER_1G_DIGCTL_3_4 0x14 5461 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 5462 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 5463 #define MDIO_OVER_1G_UP1 0x19 5464 #define MDIO_OVER_1G_UP1_2_5G 0x0001 5465 #define MDIO_OVER_1G_UP1_5G 0x0002 5466 #define MDIO_OVER_1G_UP1_6G 0x0004 5467 #define MDIO_OVER_1G_UP1_10G 0x0010 5468 #define MDIO_OVER_1G_UP1_10GH 0x0008 5469 #define MDIO_OVER_1G_UP1_12G 0x0020 5470 #define MDIO_OVER_1G_UP1_12_5G 0x0040 5471 #define MDIO_OVER_1G_UP1_13G 0x0080 5472 #define MDIO_OVER_1G_UP1_15G 0x0100 5473 #define MDIO_OVER_1G_UP1_16G 0x0200 5474 #define MDIO_OVER_1G_UP2 0x1A 5475 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 5476 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 5477 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 5478 #define MDIO_OVER_1G_UP3 0x1B 5479 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 5480 #define MDIO_OVER_1G_LP_UP1 0x1C 5481 #define MDIO_OVER_1G_LP_UP2 0x1D 5482 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 5483 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 5484 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 5485 #define MDIO_OVER_1G_LP_UP3 0x1E 5486 5487 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 5488 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 5489 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 5490 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 5491 5492 #define MDIO_REG_BANK_CL73_USERB0 0x8370 5493 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 5494 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 5495 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 5496 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 5497 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 5498 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 5499 5500 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 5501 #define MDIO_AER_BLOCK_AER_REG 0x1E 5502 5503 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 5504 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 5505 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 5506 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 5507 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 5508 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 5509 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 5510 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 5511 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 5512 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 5513 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 5514 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 5515 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 5516 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 5517 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 5518 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 5519 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 5520 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 5521 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 5522 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 5523 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 5524 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 5525 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 5526 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 5527 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 5528 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 5529 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 5530 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 5531 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 5532 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 5533 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 5534 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then 5535 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 5536 Theotherbitsarereservedandshouldbezero*/ 5537 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 5538 5539 5540 #define MDIO_PMA_DEVAD 0x1 5541 /*ieee*/ 5542 #define MDIO_PMA_REG_CTRL 0x0 5543 #define MDIO_PMA_REG_STATUS 0x1 5544 #define MDIO_PMA_REG_10G_CTRL2 0x7 5545 #define MDIO_PMA_REG_RX_SD 0xa 5546 /*bcm*/ 5547 #define MDIO_PMA_REG_BCM_CTRL 0x0096 5548 #define MDIO_PMA_REG_FEC_CTRL 0x00ab 5549 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000 5550 #define MDIO_PMA_REG_LASI_CTRL 0x9002 5551 #define MDIO_PMA_REG_RX_ALARM 0x9003 5552 #define MDIO_PMA_REG_TX_ALARM 0x9004 5553 #define MDIO_PMA_REG_LASI_STATUS 0x9005 5554 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 5555 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 5556 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 5557 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 5558 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 5559 #define MDIO_PMA_REG_MISC_CTRL 0xca0a 5560 #define MDIO_PMA_REG_GEN_CTRL 0xca10 5561 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 5562 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 5563 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 5564 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 5565 #define MDIO_PMA_REG_ROM_VER1 0xca19 5566 #define MDIO_PMA_REG_ROM_VER2 0xca1a 5567 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 5568 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 5569 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 5570 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 5571 5572 #define MDIO_PMA_REG_7101_RESET 0xc000 5573 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 5574 #define MDIO_PMA_REG_7101_VER1 0xc026 5575 #define MDIO_PMA_REG_7101_VER2 0xc027 5576 5577 5578 #define MDIO_WIS_DEVAD 0x2 5579 /*bcm*/ 5580 #define MDIO_WIS_REG_LASI_CNTL 0x9002 5581 #define MDIO_WIS_REG_LASI_STATUS 0x9005 5582 5583 #define MDIO_PCS_DEVAD 0x3 5584 #define MDIO_PCS_REG_STATUS 0x0020 5585 #define MDIO_PCS_REG_LASI_STATUS 0x9005 5586 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 5587 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 5588 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 5589 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 5590 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 5591 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 5592 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 5593 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 5594 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 5595 5596 5597 #define MDIO_XS_DEVAD 0x4 5598 #define MDIO_XS_PLL_SEQUENCER 0x8000 5599 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 5600 5601 #define MDIO_AN_DEVAD 0x7 5602 /*ieee*/ 5603 #define MDIO_AN_REG_CTRL 0x0000 5604 #define MDIO_AN_REG_STATUS 0x0001 5605 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 5606 #define MDIO_AN_REG_ADV_PAUSE 0x0010 5607 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 5608 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 5609 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 5610 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 5611 #define MDIO_AN_REG_ADV 0x0011 5612 #define MDIO_AN_REG_ADV2 0x0012 5613 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 5614 #define MDIO_AN_REG_MASTER_STATUS 0x0021 5615 /*bcm*/ 5616 #define MDIO_AN_REG_LINK_STATUS 0x8304 5617 #define MDIO_AN_REG_CL37_CL73 0x8370 5618 #define MDIO_AN_REG_CL37_AN 0xffe0 5619 #define MDIO_AN_REG_CL37_FC_LD 0xffe4 5620 #define MDIO_AN_REG_CL37_FC_LP 0xffe5 5621 5622 5623 #define IGU_FUNC_BASE 0x0400 5624 5625 #define IGU_ADDR_MSIX 0x0000 5626 #define IGU_ADDR_INT_ACK 0x0200 5627 #define IGU_ADDR_PROD_UPD 0x0201 5628 #define IGU_ADDR_ATTN_BITS_UPD 0x0202 5629 #define IGU_ADDR_ATTN_BITS_SET 0x0203 5630 #define IGU_ADDR_ATTN_BITS_CLR 0x0204 5631 #define IGU_ADDR_COALESCE_NOW 0x0205 5632 #define IGU_ADDR_SIMD_MASK 0x0206 5633 #define IGU_ADDR_SIMD_NOMASK 0x0207 5634 #define IGU_ADDR_MSI_CTL 0x0210 5635 #define IGU_ADDR_MSI_ADDR_LO 0x0211 5636 #define IGU_ADDR_MSI_ADDR_HI 0x0212 5637 #define IGU_ADDR_MSI_DATA 0x0213 5638 5639 #define IGU_INT_ENABLE 0 5640 #define IGU_INT_DISABLE 1 5641 #define IGU_INT_NOP 2 5642 #define IGU_INT_NOP2 3 5643 5644 #define COMMAND_REG_INT_ACK 0x0 5645 #define COMMAND_REG_PROD_UPD 0x4 5646 #define COMMAND_REG_ATTN_BITS_UPD 0x8 5647 #define COMMAND_REG_ATTN_BITS_SET 0xc 5648 #define COMMAND_REG_ATTN_BITS_CLR 0x10 5649 #define COMMAND_REG_COALESCE_NOW 0x14 5650 #define COMMAND_REG_SIMD_MASK 0x18 5651 #define COMMAND_REG_SIMD_NOMASK 0x1c 5652 5653 5654