Searched refs:SET_BIT (Results 1 – 6 of 6) sorted by relevance
34 tmp |= SET_BIT(8); in DisableVGA()43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
104 tmp &= ~SET_BIT(31); in InitialiseRamdac()152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
299 tmp |= SET_BIT(14); in SetCoreClockPLL()309 tmp |= SET_BIT(14); in SetCoreClockPLL()317 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()321 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()293 tmp |= SET_BIT(7); in EnableOverlayPlane()298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
31 #define SET_BIT(n) (1<<(n)) macro
248 #define SET_BIT 0 macro261 case SET_BIT: in S24C16_set_bit()285 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()297 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()307 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()501 #undef SET_BIT