1 /*
2 * drivers/mtd/nand/rtc_from4.c
3 *
4 * Copyright (C) 2004 Red Hat, Inc.
5 *
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the AG-AND flash device found on the
15 * Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
16 * which utilizes the Renesas HN29V1G91T-30 part.
17 * This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/rslib.h>
25 #include <linux/bitrev.h>
26 #include <linux/module.h>
27 #include <linux/mtd/compatmac.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <asm/io.h>
32
33 /*
34 * MTD structure for Renesas board
35 */
36 static struct mtd_info *rtc_from4_mtd = NULL;
37
38 #define RTC_FROM4_MAX_CHIPS 2
39
40 /* HS77x9 processor register defines */
41 #define SH77X9_BCR1 ((volatile unsigned short *)(0xFFFFFF60))
42 #define SH77X9_BCR2 ((volatile unsigned short *)(0xFFFFFF62))
43 #define SH77X9_WCR1 ((volatile unsigned short *)(0xFFFFFF64))
44 #define SH77X9_WCR2 ((volatile unsigned short *)(0xFFFFFF66))
45 #define SH77X9_MCR ((volatile unsigned short *)(0xFFFFFF68))
46 #define SH77X9_PCR ((volatile unsigned short *)(0xFFFFFF6C))
47 #define SH77X9_FRQCR ((volatile unsigned short *)(0xFFFFFF80))
48
49 /*
50 * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
51 */
52 /* Address where flash is mapped */
53 #define RTC_FROM4_FIO_BASE 0x14000000
54
55 /* CLE and ALE are tied to address lines 5 & 4, respectively */
56 #define RTC_FROM4_CLE (1 << 5)
57 #define RTC_FROM4_ALE (1 << 4)
58
59 /* address lines A24-A22 used for chip selection */
60 #define RTC_FROM4_NAND_ADDR_SLOT3 (0x00800000)
61 #define RTC_FROM4_NAND_ADDR_SLOT4 (0x00C00000)
62 #define RTC_FROM4_NAND_ADDR_FPGA (0x01000000)
63 /* mask address lines A24-A22 used for chip selection */
64 #define RTC_FROM4_NAND_ADDR_MASK (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
65
66 /* FPGA status register for checking device ready (bit zero) */
67 #define RTC_FROM4_FPGA_SR (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
68 #define RTC_FROM4_DEVICE_READY 0x0001
69
70 /* FPGA Reed-Solomon ECC Control register */
71
72 #define RTC_FROM4_RS_ECC_CTL (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
73 #define RTC_FROM4_RS_ECC_CTL_CLR (1 << 7)
74 #define RTC_FROM4_RS_ECC_CTL_GEN (1 << 6)
75 #define RTC_FROM4_RS_ECC_CTL_FD_E (1 << 5)
76
77 /* FPGA Reed-Solomon ECC code base */
78 #define RTC_FROM4_RS_ECC (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
79 #define RTC_FROM4_RS_ECCN (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
80
81 /* FPGA Reed-Solomon ECC check register */
82 #define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
83 #define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7)
84
85 #define ERR_STAT_ECC_AVAILABLE 0x20
86
87 /* Undefine for software ECC */
88 #define RTC_FROM4_HWECC 1
89
90 /* Define as 1 for no virtual erase blocks (in JFFS2) */
91 #define RTC_FROM4_NO_VIRTBLOCKS 0
92
93 /*
94 * Module stuff
95 */
96 static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
97
98 static const struct mtd_partition partition_info[] = {
99 {
100 .name = "Renesas flash partition 1",
101 .offset = 0,
102 .size = MTDPART_SIZ_FULL},
103 };
104
105 #define NUM_PARTITIONS 1
106
107 /*
108 * hardware specific flash bbt decriptors
109 * Note: this is to allow debugging by disabling
110 * NAND_BBT_CREATE and/or NAND_BBT_WRITE
111 *
112 */
113 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
114 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
115
116 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
117 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
118 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
119 .offs = 40,
120 .len = 4,
121 .veroffs = 44,
122 .maxblocks = 4,
123 .pattern = bbt_pattern
124 };
125
126 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
127 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
128 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
129 .offs = 40,
130 .len = 4,
131 .veroffs = 44,
132 .maxblocks = 4,
133 .pattern = mirror_pattern
134 };
135
136 #ifdef RTC_FROM4_HWECC
137
138 /* the Reed Solomon control structure */
139 static struct rs_control *rs_decoder;
140
141 /*
142 * hardware specific Out Of Band information
143 */
144 static struct nand_ecclayout rtc_from4_nand_oobinfo = {
145 .eccbytes = 32,
146 .eccpos = {
147 0, 1, 2, 3, 4, 5, 6, 7,
148 8, 9, 10, 11, 12, 13, 14, 15,
149 16, 17, 18, 19, 20, 21, 22, 23,
150 24, 25, 26, 27, 28, 29, 30, 31},
151 .oobfree = {{32, 32}}
152 };
153
154 #endif
155
156 /*
157 * rtc_from4_hwcontrol - hardware specific access to control-lines
158 * @mtd: MTD device structure
159 * @cmd: hardware control command
160 *
161 * Address lines (A5 and A4) are used to control Command and Address Latch
162 * Enable on this board, so set the read/write address appropriately.
163 *
164 * Chip Enable is also controlled by the Chip Select (CS5) and
165 * Address lines (A24-A22), so no action is required here.
166 *
167 */
rtc_from4_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)168 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,
169 unsigned int ctrl)
170 {
171 struct nand_chip *chip = (mtd->priv);
172
173 if (cmd == NAND_CMD_NONE)
174 return;
175
176 if (ctrl & NAND_CLE)
177 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);
178 else
179 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);
180 }
181
182 /*
183 * rtc_from4_nand_select_chip - hardware specific chip select
184 * @mtd: MTD device structure
185 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
186 *
187 * The chip select is based on address lines A24-A22.
188 * This driver uses flash slots 3 and 4 (A23-A22).
189 *
190 */
rtc_from4_nand_select_chip(struct mtd_info * mtd,int chip)191 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
192 {
193 struct nand_chip *this = mtd->priv;
194
195 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
196 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
197
198 switch (chip) {
199
200 case 0: /* select slot 3 chip */
201 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
202 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
203 break;
204 case 1: /* select slot 4 chip */
205 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
206 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
207 break;
208
209 }
210 }
211
212 /*
213 * rtc_from4_nand_device_ready - hardware specific ready/busy check
214 * @mtd: MTD device structure
215 *
216 * This board provides the Ready/Busy state in the status register
217 * of the FPGA. Bit zero indicates the RDY(1)/BSY(0) signal.
218 *
219 */
rtc_from4_nand_device_ready(struct mtd_info * mtd)220 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
221 {
222 unsigned short status;
223
224 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
225
226 return (status & RTC_FROM4_DEVICE_READY);
227
228 }
229
230 /*
231 * deplete - code to perform device recovery in case there was a power loss
232 * @mtd: MTD device structure
233 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
234 *
235 * If there was a sudden loss of power during an erase operation, a
236 * "device recovery" operation must be performed when power is restored
237 * to ensure correct operation. This routine performs the required steps
238 * for the requested chip.
239 *
240 * See page 86 of the data sheet for details.
241 *
242 */
deplete(struct mtd_info * mtd,int chip)243 static void deplete(struct mtd_info *mtd, int chip)
244 {
245 struct nand_chip *this = mtd->priv;
246
247 /* wait until device is ready */
248 while (!this->dev_ready(mtd)) ;
249
250 this->select_chip(mtd, chip);
251
252 /* Send the commands for device recovery, phase 1 */
253 this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
254 this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
255
256 /* Send the commands for device recovery, phase 2 */
257 this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
258 this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
259
260 }
261
262 #ifdef RTC_FROM4_HWECC
263 /*
264 * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
265 * @mtd: MTD device structure
266 * @mode: I/O mode; read or write
267 *
268 * enable hardware ECC for data read or write
269 *
270 */
rtc_from4_enable_hwecc(struct mtd_info * mtd,int mode)271 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
272 {
273 volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
274 unsigned short status;
275
276 switch (mode) {
277 case NAND_ECC_READ:
278 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;
279
280 *rs_ecc_ctl = status;
281 break;
282
283 case NAND_ECC_READSYN:
284 status = 0x00;
285
286 *rs_ecc_ctl = status;
287 break;
288
289 case NAND_ECC_WRITE:
290 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_GEN | RTC_FROM4_RS_ECC_CTL_FD_E;
291
292 *rs_ecc_ctl = status;
293 break;
294
295 default:
296 BUG();
297 break;
298 }
299
300 }
301
302 /*
303 * rtc_from4_calculate_ecc - hardware specific code to read ECC code
304 * @mtd: MTD device structure
305 * @dat: buffer containing the data to generate ECC codes
306 * @ecc_code ECC codes calculated
307 *
308 * The ECC code is calculated by the FPGA. All we have to do is read the values
309 * from the FPGA registers.
310 *
311 * Note: We read from the inverted registers, since data is inverted before
312 * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
313 *
314 */
rtc_from4_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)315 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
316 {
317 volatile unsigned short *rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
318 unsigned short value;
319 int i;
320
321 for (i = 0; i < 8; i++) {
322 value = *rs_eccn;
323 ecc_code[i] = (unsigned char)value;
324 rs_eccn++;
325 }
326 ecc_code[7] |= 0x0f; /* set the last four bits (not used) */
327 }
328
329 /*
330 * rtc_from4_correct_data - hardware specific code to correct data using ECC code
331 * @mtd: MTD device structure
332 * @buf: buffer containing the data to generate ECC codes
333 * @ecc1 ECC codes read
334 * @ecc2 ECC codes calculated
335 *
336 * The FPGA tells us fast, if there's an error or not. If no, we go back happy
337 * else we read the ecc results from the fpga and call the rs library to decode
338 * and hopefully correct the error.
339 *
340 */
rtc_from4_correct_data(struct mtd_info * mtd,const u_char * buf,u_char * ecc1,u_char * ecc2)341 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
342 {
343 int i, j, res;
344 unsigned short status;
345 uint16_t par[6], syn[6];
346 uint8_t ecc[8];
347 volatile unsigned short *rs_ecc;
348
349 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
350
351 if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
352 return 0;
353 }
354
355 /* Read the syndrom pattern from the FPGA and correct the bitorder */
356 rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
357 for (i = 0; i < 8; i++) {
358 ecc[i] = bitrev8(*rs_ecc);
359 rs_ecc++;
360 }
361
362 /* convert into 6 10bit syndrome fields */
363 par[5] = rs_decoder->index_of[(((uint16_t) ecc[0] >> 0) & 0x0ff) | (((uint16_t) ecc[1] << 8) & 0x300)];
364 par[4] = rs_decoder->index_of[(((uint16_t) ecc[1] >> 2) & 0x03f) | (((uint16_t) ecc[2] << 6) & 0x3c0)];
365 par[3] = rs_decoder->index_of[(((uint16_t) ecc[2] >> 4) & 0x00f) | (((uint16_t) ecc[3] << 4) & 0x3f0)];
366 par[2] = rs_decoder->index_of[(((uint16_t) ecc[3] >> 6) & 0x003) | (((uint16_t) ecc[4] << 2) & 0x3fc)];
367 par[1] = rs_decoder->index_of[(((uint16_t) ecc[5] >> 0) & 0x0ff) | (((uint16_t) ecc[6] << 8) & 0x300)];
368 par[0] = (((uint16_t) ecc[6] >> 2) & 0x03f) | (((uint16_t) ecc[7] << 6) & 0x3c0);
369
370 /* Convert to computable syndrome */
371 for (i = 0; i < 6; i++) {
372 syn[i] = par[0];
373 for (j = 1; j < 6; j++)
374 if (par[j] != rs_decoder->nn)
375 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
376
377 /* Convert to index form */
378 syn[i] = rs_decoder->index_of[syn[i]];
379 }
380
381 /* Let the library code do its magic. */
382 res = decode_rs8(rs_decoder, (uint8_t *) buf, par, 512, syn, 0, NULL, 0xff, NULL);
383 if (res > 0) {
384 DEBUG(MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " "ECC corrected %d errors on read\n", res);
385 }
386 return res;
387 }
388
389 /**
390 * rtc_from4_errstat - perform additional error status checks
391 * @mtd: MTD device structure
392 * @this: NAND chip structure
393 * @state: state or the operation
394 * @status: status code returned from read status
395 * @page: startpage inside the chip, must be called with (page & this->pagemask)
396 *
397 * Perform additional error status checks on erase and write failures
398 * to determine if errors are correctable. For this device, correctable
399 * 1-bit errors on erase and write are considered acceptable.
400 *
401 * note: see pages 34..37 of data sheet for details.
402 *
403 */
rtc_from4_errstat(struct mtd_info * mtd,struct nand_chip * this,int state,int status,int page)404 static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this,
405 int state, int status, int page)
406 {
407 int er_stat = 0;
408 int rtn, retlen;
409 size_t len;
410 uint8_t *buf;
411 int i;
412
413 this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
414
415 if (state == FL_ERASING) {
416
417 for (i = 0; i < 4; i++) {
418 if (!(status & 1 << (i + 1)))
419 continue;
420 this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1),
421 -1, -1);
422 rtn = this->read_byte(mtd);
423 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
424
425 /* err_ecc_not_avail */
426 if (!(rtn & ERR_STAT_ECC_AVAILABLE))
427 er_stat |= 1 << (i + 1);
428 }
429
430 } else if (state == FL_WRITING) {
431
432 unsigned long corrected = mtd->ecc_stats.corrected;
433
434 /* single bank write logic */
435 this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1);
436 rtn = this->read_byte(mtd);
437 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
438
439 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
440 /* err_ecc_not_avail */
441 er_stat |= 1 << 1;
442 goto out;
443 }
444
445 len = mtd->writesize;
446 buf = kmalloc(len, GFP_KERNEL);
447 if (!buf) {
448 printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
449 er_stat = 1;
450 goto out;
451 }
452
453 /* recovery read */
454 rtn = nand_do_read(mtd, page, len, &retlen, buf);
455
456 /* if read failed or > 1-bit error corrected */
457 if (rtn || (mtd->ecc_stats.corrected - corrected) > 1)
458 er_stat |= 1 << 1;
459 kfree(buf);
460 }
461 out:
462 rtn = status;
463 if (er_stat == 0) { /* if ECC is available */
464 rtn = (status & ~NAND_STATUS_FAIL); /* clear the error bit */
465 }
466
467 return rtn;
468 }
469 #endif
470
471 /*
472 * Main initialization routine
473 */
rtc_from4_init(void)474 static int __init rtc_from4_init(void)
475 {
476 struct nand_chip *this;
477 unsigned short bcr1, bcr2, wcr2;
478 int i;
479 int ret;
480
481 /* Allocate memory for MTD device structure and private data */
482 rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
483 if (!rtc_from4_mtd) {
484 printk("Unable to allocate Renesas NAND MTD device structure.\n");
485 return -ENOMEM;
486 }
487
488 /* Get pointer to private data */
489 this = (struct nand_chip *)(&rtc_from4_mtd[1]);
490
491 /* Initialize structures */
492 memset(rtc_from4_mtd, 0, sizeof(struct mtd_info));
493 memset(this, 0, sizeof(struct nand_chip));
494
495 /* Link the private data with the MTD structure */
496 rtc_from4_mtd->priv = this;
497 rtc_from4_mtd->owner = THIS_MODULE;
498
499 /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
500 bcr1 = *SH77X9_BCR1 & ~0x0002;
501 bcr1 |= 0x0002;
502 *SH77X9_BCR1 = bcr1;
503
504 /* set */
505 bcr2 = *SH77X9_BCR2 & ~0x0c00;
506 bcr2 |= 0x0800;
507 *SH77X9_BCR2 = bcr2;
508
509 /* set area 5 wait states */
510 wcr2 = *SH77X9_WCR2 & ~0x1c00;
511 wcr2 |= 0x1c00;
512 *SH77X9_WCR2 = wcr2;
513
514 /* Set address of NAND IO lines */
515 this->IO_ADDR_R = rtc_from4_fio_base;
516 this->IO_ADDR_W = rtc_from4_fio_base;
517 /* Set address of hardware control function */
518 this->cmd_ctrl = rtc_from4_hwcontrol;
519 /* Set address of chip select function */
520 this->select_chip = rtc_from4_nand_select_chip;
521 /* command delay time (in us) */
522 this->chip_delay = 100;
523 /* return the status of the Ready/Busy line */
524 this->dev_ready = rtc_from4_nand_device_ready;
525
526 #ifdef RTC_FROM4_HWECC
527 printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
528
529 this->ecc.mode = NAND_ECC_HW_SYNDROME;
530 this->ecc.size = 512;
531 this->ecc.bytes = 8;
532 /* return the status of extra status and ECC checks */
533 this->errstat = rtc_from4_errstat;
534 /* set the nand_oobinfo to support FPGA H/W error detection */
535 this->ecc.layout = &rtc_from4_nand_oobinfo;
536 this->ecc.hwctl = rtc_from4_enable_hwecc;
537 this->ecc.calculate = rtc_from4_calculate_ecc;
538 this->ecc.correct = rtc_from4_correct_data;
539
540 /* We could create the decoder on demand, if memory is a concern.
541 * This way we have it handy, if an error happens
542 *
543 * Symbolsize is 10 (bits)
544 * Primitve polynomial is x^10+x^3+1
545 * first consecutive root is 0
546 * primitve element to generate roots = 1
547 * generator polinomial degree = 6
548 */
549 rs_decoder = init_rs(10, 0x409, 0, 1, 6);
550 if (!rs_decoder) {
551 printk(KERN_ERR "Could not create a RS decoder\n");
552 ret = -ENOMEM;
553 goto err_1;
554 }
555 #else
556 printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
557
558 this->ecc.mode = NAND_ECC_SOFT;
559 #endif
560
561 /* set the bad block tables to support debugging */
562 this->bbt_td = &rtc_from4_bbt_main_descr;
563 this->bbt_md = &rtc_from4_bbt_mirror_descr;
564
565 /* Scan to find existence of the device */
566 if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
567 ret = -ENXIO;
568 goto err_2;
569 }
570
571 /* Perform 'device recovery' for each chip in case there was a power loss. */
572 for (i = 0; i < this->numchips; i++) {
573 deplete(rtc_from4_mtd, i);
574 }
575
576 #if RTC_FROM4_NO_VIRTBLOCKS
577 /* use a smaller erase block to minimize wasted space when a block is bad */
578 /* note: this uses eight times as much RAM as using the default and makes */
579 /* mounts take four times as long. */
580 rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;
581 #endif
582
583 /* Register the partitions */
584 ret = add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
585 if (ret)
586 goto err_3;
587
588 /* Return happy */
589 return 0;
590 err_3:
591 nand_release(rtc_from4_mtd);
592 err_2:
593 free_rs(rs_decoder);
594 err_1:
595 kfree(rtc_from4_mtd);
596 return ret;
597 }
598
599 module_init(rtc_from4_init);
600
601 /*
602 * Clean up routine
603 */
rtc_from4_cleanup(void)604 static void __exit rtc_from4_cleanup(void)
605 {
606 /* Release resource, unregister partitions */
607 nand_release(rtc_from4_mtd);
608
609 /* Free the MTD device structure */
610 kfree(rtc_from4_mtd);
611
612 #ifdef RTC_FROM4_HWECC
613 /* Free the reed solomon resources */
614 if (rs_decoder) {
615 free_rs(rs_decoder);
616 }
617 #endif
618 }
619
620 module_exit(rtc_from4_cleanup);
621
622 MODULE_LICENSE("GPL");
623 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
624 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");
625