Searched refs:clock_speed (Results 1 – 5 of 5) sorted by relevance
| /drivers/char/ |
| D | synclink_gt.c | 357 .clock_speed = 0,
1136 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; in get_params32()
1163 info->params.clock_speed = tmp_params.clock_speed; in set_params32()
1649 new_line.clock_rate = info->params.clock_speed; in hdlcdev_ioctl()
1689 info->params.clock_speed = new_line.clock_rate; in hdlcdev_ioctl()
1691 info->params.clock_speed = 0; in hdlcdev_ioctl()
3771 if (info->params.clock_speed) in enable_loopback()
3772 set_rate(info, info->params.clock_speed); in enable_loopback()
4253 if (info->params.clock_speed) in sync_mode()
4274 set_rate(info, info->params.clock_speed * 16); in sync_mode()
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| D | synclinkmp.c | 1790 new_line.clock_rate = info->params.clock_speed; in hdlcdev_ioctl()
1830 info->params.clock_speed = new_line.clock_rate; in hdlcdev_ioctl()
1832 info->params.clock_speed = 0; in hdlcdev_ioctl()
4065 if (info->params.clock_speed) in enable_loopback()
4066 set_rate(info, info->params.clock_speed); in enable_loopback()
4629 set_rate(info, info->params.clock_speed * DpllDivisor); in hdlc_mode()
4631 set_rate(info, info->params.clock_speed); in hdlc_mode()
4715 set_rate(info, info->params.clock_speed); in hdlc_mode()
5255 u32 speed = info->params.clock_speed; in loopback_test()
5257 info->params.clock_speed = 3686400; in loopback_test()
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| D | synclink.c | 5010 if ( info->params.clock_speed ) in usc_set_sdlc_mode()
5012 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed); in usc_set_sdlc_mode()
5013 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2) in usc_set_sdlc_mode()
5014 / info->params.clock_speed) ) in usc_set_sdlc_mode()
5255 if (info->params.clock_speed) { in usc_enable_loopback()
5257 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); in usc_enable_loopback()
5259 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1)); in usc_enable_loopback()
6172 usc_enable_aux_clock(info, info->params.clock_speed); in usc_set_sync_mode()
7890 new_line.clock_rate = info->params.clock_speed; in hdlcdev_ioctl()
7930 info->params.clock_speed = new_line.clock_rate; in hdlcdev_ioctl()
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| /drivers/char/pcmcia/ |
| D | synclink_cs.c | 3009 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) in enable_auxclk()
3050 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) in enable_auxclk()
3071 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed) in enable_auxclk()
3072 mgslpc_set_rate(info, CHB, info->params.clock_speed); in enable_auxclk()
3090 if (info->params.clock_speed) in loopback_enable()
3091 mgslpc_set_rate(info, CHA, info->params.clock_speed); in loopback_enable()
3278 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16); in hdlc_mode()
3280 mgslpc_set_rate(info, CHA, info->params.clock_speed); in hdlc_mode()
4192 new_line.clock_rate = info->params.clock_speed; in hdlcdev_ioctl()
4232 info->params.clock_speed = new_line.clock_rate; in hdlcdev_ioctl()
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| /drivers/scsi/ |
| D | dc395x.c | 448 static u16 clock_speed[] = { 200, 133, 100, 80, 67, 58, 50, 40 }; variable
4239 clock_speed[eeprom->target[0].period] / 10, in print_eeprom_settings()
4240 clock_speed[eeprom->target[0].period] % 10, in print_eeprom_settings()
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