1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 */
29
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
32
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
44 #include <linux/ip.h>
45 #include <linux/in.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48
49 #include <linux/ethtool.h>
50 #include <linux/mii.h>
51 #include <linux/interrupt.h>
52 #include <linux/timer.h>
53
54 #include <linux/mm.h>
55 #include <linux/mman.h>
56 #include <linux/vmalloc.h>
57
58 #include <asm/system.h>
59 #include <asm/io.h>
60 #include <asm/byteorder.h>
61 #include <asm/uaccess.h>
62 #include <asm/pgtable.h>
63
64 #include "netxen_nic_hw.h"
65
66 #define _NETXEN_NIC_LINUX_MAJOR 4
67 #define _NETXEN_NIC_LINUX_MINOR 0
68 #define _NETXEN_NIC_LINUX_SUBVERSION 11
69 #define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
70
71 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
72
73 #define NETXEN_NUM_FLASH_SECTORS (64)
74 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
75 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
76 * NETXEN_FLASH_SECTOR_SIZE)
77
78 #define PHAN_VENDOR_ID 0x4040
79
80 #define RCV_DESC_RINGSIZE \
81 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
82 #define STATUS_DESC_RINGSIZE \
83 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
84 #define LRO_DESC_RINGSIZE \
85 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
86 #define TX_RINGSIZE \
87 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
88 #define RCV_BUFFSIZE \
89 (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
90 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
91
92 #define NETXEN_NETDEV_STATUS 0x1
93 #define NETXEN_RCV_PRODUCER_OFFSET 0
94 #define NETXEN_RCV_PEG_DB_ID 2
95 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
96 #define FLASH_SUCCESS 0
97
98 #define ADDR_IN_WINDOW1(off) \
99 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
100
101 /*
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
105 #define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
107
108 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
111 #define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114 #define NX_P2_C0 0x24
115 #define NX_P2_C1 0x25
116 #define NX_P3_A0 0x30
117 #define NX_P3_A2 0x30
118 #define NX_P3_B0 0x40
119 #define NX_P3_B1 0x41
120
121 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
122 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
123
124 #define FIRST_PAGE_GROUP_START 0
125 #define FIRST_PAGE_GROUP_END 0x100000
126
127 #define SECOND_PAGE_GROUP_START 0x6000000
128 #define SECOND_PAGE_GROUP_END 0x68BC000
129
130 #define THIRD_PAGE_GROUP_START 0x70E4000
131 #define THIRD_PAGE_GROUP_END 0x8000000
132
133 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
134 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
135 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
136
137 #define P2_MAX_MTU (8000)
138 #define P3_MAX_MTU (9600)
139 #define NX_ETHERMTU 1500
140 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
141
142 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
143 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
144 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
145 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
146
147 #define MAX_RX_BUFFER_LENGTH 1760
148 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
149 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
150 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
151 #define RX_JUMBO_DMA_MAP_LEN \
152 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
153 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
154
155 /*
156 * Maximum number of ring contexts
157 */
158 #define MAX_RING_CTX 1
159
160 /* Opcodes to be used with the commands */
161 #define TX_ETHER_PKT 0x01
162 #define TX_TCP_PKT 0x02
163 #define TX_UDP_PKT 0x03
164 #define TX_IP_PKT 0x04
165 #define TX_TCP_LSO 0x05
166 #define TX_TCP_LSO6 0x06
167 #define TX_IPSEC 0x07
168 #define TX_IPSEC_CMD 0x0a
169 #define TX_TCPV6_PKT 0x0b
170 #define TX_UDPV6_PKT 0x0c
171
172 /* The following opcodes are for internal consumption. */
173 #define NETXEN_CONTROL_OP 0x10
174 #define PEGNET_REQUEST 0x11
175
176 #define MAX_NUM_CARDS 4
177
178 #define MAX_BUFFERS_PER_CMD 32
179
180 /*
181 * Following are the states of the Phantom. Phantom will set them and
182 * Host will read to check if the fields are correct.
183 */
184 #define PHAN_INITIALIZE_START 0xff00
185 #define PHAN_INITIALIZE_FAILED 0xffff
186 #define PHAN_INITIALIZE_COMPLETE 0xff01
187
188 /* Host writes the following to notify that it has done the init-handshake */
189 #define PHAN_INITIALIZE_ACK 0xf00f
190
191 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
192
193 /* descriptor types */
194 #define RCV_DESC_NORMAL 0x01
195 #define RCV_DESC_JUMBO 0x02
196 #define RCV_DESC_LRO 0x04
197 #define RCV_DESC_NORMAL_CTXID 0
198 #define RCV_DESC_JUMBO_CTXID 1
199 #define RCV_DESC_LRO_CTXID 2
200
201 #define RCV_DESC_TYPE(ID) \
202 ((ID == RCV_DESC_JUMBO_CTXID) \
203 ? RCV_DESC_JUMBO \
204 : ((ID == RCV_DESC_LRO_CTXID) \
205 ? RCV_DESC_LRO : \
206 (RCV_DESC_NORMAL)))
207
208 #define MAX_CMD_DESCRIPTORS 4096
209 #define MAX_RCV_DESCRIPTORS 16384
210 #define MAX_CMD_DESCRIPTORS_HOST 1024
211 #define MAX_RCV_DESCRIPTORS_1G 2048
212 #define MAX_RCV_DESCRIPTORS_10G 4096
213 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
214 #define MAX_LRO_RCV_DESCRIPTORS 8
215 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
216 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
217 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
218 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
219 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
220 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
221 MAX_LRO_RCV_DESCRIPTORS)
222 #define MIN_TX_COUNT 4096
223 #define MIN_RX_COUNT 4096
224 #define NETXEN_CTX_SIGNATURE 0xdee0
225 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
226 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
227
228 #define PHAN_PEG_RCV_INITIALIZED 0xff01
229 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
230
231 #define get_next_index(index, length) \
232 (((index) + 1) & ((length) - 1))
233
234 #define get_index_range(index,length,count) \
235 (((index) + (count)) & ((length) - 1))
236
237 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
238 #define MPORT_MULTI_FUNCTION_MODE 0x2222
239
240 #include "netxen_nic_phan_reg.h"
241
242 /*
243 * NetXen host-peg signal message structure
244 *
245 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
246 * Bit 2 : priv_id => must be 1
247 * Bit 3-17 : count => for doorbell
248 * Bit 18-27 : ctx_id => Context id
249 * Bit 28-31 : opcode
250 */
251
252 typedef u32 netxen_ctx_msg;
253
254 #define netxen_set_msg_peg_id(config_word, val) \
255 ((config_word) &= ~3, (config_word) |= val & 3)
256 #define netxen_set_msg_privid(config_word) \
257 ((config_word) |= 1 << 2)
258 #define netxen_set_msg_count(config_word, val) \
259 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
260 #define netxen_set_msg_ctxid(config_word, val) \
261 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
262 #define netxen_set_msg_opcode(config_word, val) \
263 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
264
265 struct netxen_rcv_context {
266 __le64 rcv_ring_addr;
267 __le32 rcv_ring_size;
268 __le32 rsrvd;
269 };
270
271 struct netxen_ring_ctx {
272
273 /* one command ring */
274 __le64 cmd_consumer_offset;
275 __le64 cmd_ring_addr;
276 __le32 cmd_ring_size;
277 __le32 rsrvd;
278
279 /* three receive rings */
280 struct netxen_rcv_context rcv_ctx[3];
281
282 /* one status ring */
283 __le64 sts_ring_addr;
284 __le32 sts_ring_size;
285
286 __le32 ctx_id;
287 } __attribute__ ((aligned(64)));
288
289 /*
290 * Following data structures describe the descriptors that will be used.
291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
292 * we are doing LSO (above the 1500 size packet) only.
293 */
294
295 /*
296 * The size of reference handle been changed to 16 bits to pass the MSS fields
297 * for the LSO packet
298 */
299
300 #define FLAGS_CHECKSUM_ENABLED 0x01
301 #define FLAGS_LSO_ENABLED 0x02
302 #define FLAGS_IPSEC_SA_ADD 0x04
303 #define FLAGS_IPSEC_SA_DELETE 0x08
304 #define FLAGS_VLAN_TAGGED 0x10
305
306 #define netxen_set_cmd_desc_port(cmd_desc, var) \
307 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
308 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
309 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
310
311 #define netxen_set_tx_port(_desc, _port) \
312 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
313
314 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
315 (_desc)->flags_opcode = \
316 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
317
318 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
319 (_desc)->num_of_buffers_total_length = \
320 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
321
322 struct cmd_desc_type0 {
323 u8 tcp_hdr_offset; /* For LSO only */
324 u8 ip_hdr_offset; /* For LSO only */
325 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
326 __le16 flags_opcode;
327 /* Bit pattern: 0-7 total number of segments,
328 8-31 Total size of the packet */
329 __le32 num_of_buffers_total_length;
330 union {
331 struct {
332 __le32 addr_low_part2;
333 __le32 addr_high_part2;
334 };
335 __le64 addr_buffer2;
336 };
337
338 __le16 reference_handle; /* changed to u16 to add mss */
339 __le16 mss; /* passed by NDIS_PACKET for LSO */
340 /* Bit pattern 0-3 port, 0-3 ctx id */
341 u8 port_ctxid;
342 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
343 __le16 conn_id; /* IPSec offoad only */
344
345 union {
346 struct {
347 __le32 addr_low_part3;
348 __le32 addr_high_part3;
349 };
350 __le64 addr_buffer3;
351 };
352 union {
353 struct {
354 __le32 addr_low_part1;
355 __le32 addr_high_part1;
356 };
357 __le64 addr_buffer1;
358 };
359
360 __le16 buffer1_length;
361 __le16 buffer2_length;
362 __le16 buffer3_length;
363 __le16 buffer4_length;
364
365 union {
366 struct {
367 __le32 addr_low_part4;
368 __le32 addr_high_part4;
369 };
370 __le64 addr_buffer4;
371 };
372
373 __le64 unused;
374
375 } __attribute__ ((aligned(64)));
376
377 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
378 struct rcv_desc {
379 __le16 reference_handle;
380 __le16 reserved;
381 __le32 buffer_length; /* allocated buffer length (usually 2K) */
382 __le64 addr_buffer;
383 };
384
385 /* opcode field in status_desc */
386 #define NETXEN_NIC_RXPKT_DESC 0x04
387 #define NETXEN_OLD_RXPKT_DESC 0x3f
388
389 /* for status field in status_desc */
390 #define STATUS_NEED_CKSUM (1)
391 #define STATUS_CKSUM_OK (2)
392
393 /* owner bits of status_desc */
394 #define STATUS_OWNER_HOST (0x1)
395 #define STATUS_OWNER_PHANTOM (0x2)
396
397 #define NETXEN_PROT_IP (1)
398 #define NETXEN_PROT_UNKNOWN (0)
399
400 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
401
402 #define netxen_get_sts_desc_lro_cnt(status_desc) \
403 ((status_desc)->lro & 0x7F)
404 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
405 (((status_desc)->lro & 0x80) >> 7)
406
407 #define netxen_get_sts_port(sts_data) \
408 ((sts_data) & 0x0F)
409 #define netxen_get_sts_status(sts_data) \
410 (((sts_data) >> 4) & 0x0F)
411 #define netxen_get_sts_type(sts_data) \
412 (((sts_data) >> 8) & 0x0F)
413 #define netxen_get_sts_totallength(sts_data) \
414 (((sts_data) >> 12) & 0xFFFF)
415 #define netxen_get_sts_refhandle(sts_data) \
416 (((sts_data) >> 28) & 0xFFFF)
417 #define netxen_get_sts_prot(sts_data) \
418 (((sts_data) >> 44) & 0x0F)
419 #define netxen_get_sts_pkt_offset(sts_data) \
420 (((sts_data) >> 48) & 0x1F)
421 #define netxen_get_sts_opcode(sts_data) \
422 (((sts_data) >> 58) & 0x03F)
423
424 #define netxen_get_sts_owner(status_desc) \
425 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
426 #define netxen_set_sts_owner(status_desc, val) { \
427 (status_desc)->status_desc_data = \
428 ((status_desc)->status_desc_data & \
429 ~cpu_to_le64(0x3ULL << 56)) | \
430 cpu_to_le64((u64)((val) & 0x3) << 56); \
431 }
432
433 struct status_desc {
434 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
435 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
436 53-55 desc_cnt, 56-57 owner, 58-63 opcode
437 */
438 __le64 status_desc_data;
439 union {
440 struct {
441 __le32 hash_value;
442 u8 hash_type;
443 u8 msg_type;
444 u8 unused;
445 union {
446 /* Bit pattern: 0-6 lro_count indicates frag
447 * sequence, 7 last_frag indicates last frag
448 */
449 u8 lro;
450
451 /* chained buffers */
452 u8 nr_frags;
453 };
454 };
455 struct {
456 __le16 frag_handles[4];
457 };
458 };
459 } __attribute__ ((aligned(16)));
460
461 enum {
462 NETXEN_RCV_PEG_0 = 0,
463 NETXEN_RCV_PEG_1
464 };
465 /* The version of the main data structure */
466 #define NETXEN_BDINFO_VERSION 1
467
468 /* Magic number to let user know flash is programmed */
469 #define NETXEN_BDINFO_MAGIC 0x12345678
470
471 /* Max number of Gig ports on a Phantom board */
472 #define NETXEN_MAX_PORTS 4
473
474 typedef enum {
475 NETXEN_BRDTYPE_P1_BD = 0x0000,
476 NETXEN_BRDTYPE_P1_SB = 0x0001,
477 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
478 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
479
480 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
481 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
482 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
483 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
484 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
485
486 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
487 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
488 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
489
490 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
491 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
492 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
493 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
494 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
495 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
496 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
497 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
498 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
499 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
500 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
501 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
502 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
503 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
504
505 } netxen_brdtype_t;
506
507 typedef enum {
508 NETXEN_BRDMFG_INVENTEC = 1
509 } netxen_brdmfg;
510
511 typedef enum {
512 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
513 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
514 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
515 MEM_ORG_256Mbx4 = 0x3,
516 MEM_ORG_256Mbx8 = 0x4,
517 MEM_ORG_256Mbx16 = 0x5,
518 MEM_ORG_512Mbx4 = 0x6,
519 MEM_ORG_512Mbx8 = 0x7,
520 MEM_ORG_512Mbx16 = 0x8,
521 MEM_ORG_1Gbx4 = 0x9,
522 MEM_ORG_1Gbx8 = 0xa,
523 MEM_ORG_1Gbx16 = 0xb,
524 MEM_ORG_2Gbx4 = 0xc,
525 MEM_ORG_2Gbx8 = 0xd,
526 MEM_ORG_2Gbx16 = 0xe,
527 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
528 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
529 } netxen_mn_mem_org_t;
530
531 typedef enum {
532 MEM_ORG_512Kx36 = 0x0,
533 MEM_ORG_1Mx36 = 0x1,
534 MEM_ORG_2Mx36 = 0x2
535 } netxen_sn_mem_org_t;
536
537 typedef enum {
538 MEM_DEPTH_4MB = 0x1,
539 MEM_DEPTH_8MB = 0x2,
540 MEM_DEPTH_16MB = 0x3,
541 MEM_DEPTH_32MB = 0x4,
542 MEM_DEPTH_64MB = 0x5,
543 MEM_DEPTH_128MB = 0x6,
544 MEM_DEPTH_256MB = 0x7,
545 MEM_DEPTH_512MB = 0x8,
546 MEM_DEPTH_1GB = 0x9,
547 MEM_DEPTH_2GB = 0xa,
548 MEM_DEPTH_4GB = 0xb,
549 MEM_DEPTH_8GB = 0xc,
550 MEM_DEPTH_16GB = 0xd,
551 MEM_DEPTH_32GB = 0xe
552 } netxen_mem_depth_t;
553
554 struct netxen_board_info {
555 u32 header_version;
556
557 u32 board_mfg;
558 u32 board_type;
559 u32 board_num;
560 u32 chip_id;
561 u32 chip_minor;
562 u32 chip_major;
563 u32 chip_pkg;
564 u32 chip_lot;
565
566 u32 port_mask; /* available niu ports */
567 u32 peg_mask; /* available pegs */
568 u32 icache_ok; /* can we run with icache? */
569 u32 dcache_ok; /* can we run with dcache? */
570 u32 casper_ok;
571
572 u32 mac_addr_lo_0;
573 u32 mac_addr_lo_1;
574 u32 mac_addr_lo_2;
575 u32 mac_addr_lo_3;
576
577 /* MN-related config */
578 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
579 u32 mn_sync_shift_cclk;
580 u32 mn_sync_shift_mclk;
581 u32 mn_wb_en;
582 u32 mn_crystal_freq; /* in MHz */
583 u32 mn_speed; /* in MHz */
584 u32 mn_org;
585 u32 mn_depth;
586 u32 mn_ranks_0; /* ranks per slot */
587 u32 mn_ranks_1; /* ranks per slot */
588 u32 mn_rd_latency_0;
589 u32 mn_rd_latency_1;
590 u32 mn_rd_latency_2;
591 u32 mn_rd_latency_3;
592 u32 mn_rd_latency_4;
593 u32 mn_rd_latency_5;
594 u32 mn_rd_latency_6;
595 u32 mn_rd_latency_7;
596 u32 mn_rd_latency_8;
597 u32 mn_dll_val[18];
598 u32 mn_mode_reg; /* MIU DDR Mode Register */
599 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
600 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
601 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
602 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
603
604 /* SN-related config */
605 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
606 u32 sn_pt_mode; /* pass through mode */
607 u32 sn_ecc_en;
608 u32 sn_wb_en;
609 u32 sn_crystal_freq;
610 u32 sn_speed;
611 u32 sn_org;
612 u32 sn_depth;
613 u32 sn_dll_tap;
614 u32 sn_rd_latency;
615
616 u32 mac_addr_hi_0;
617 u32 mac_addr_hi_1;
618 u32 mac_addr_hi_2;
619 u32 mac_addr_hi_3;
620
621 u32 magic; /* indicates flash has been initialized */
622
623 u32 mn_rdimm;
624 u32 mn_dll_override;
625
626 };
627
628 #define FLASH_NUM_PORTS (4)
629
630 struct netxen_flash_mac_addr {
631 u32 flash_addr[32];
632 };
633
634 struct netxen_user_old_info {
635 u8 flash_md5[16];
636 u8 crbinit_md5[16];
637 u8 brdcfg_md5[16];
638 /* bootloader */
639 u32 bootld_version;
640 u32 bootld_size;
641 u8 bootld_md5[16];
642 /* image */
643 u32 image_version;
644 u32 image_size;
645 u8 image_md5[16];
646 /* primary image status */
647 u32 primary_status;
648 u32 secondary_present;
649
650 /* MAC address , 4 ports */
651 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
652 };
653 #define FLASH_NUM_MAC_PER_PORT 32
654 struct netxen_user_info {
655 u8 flash_md5[16 * 64];
656 /* bootloader */
657 u32 bootld_version;
658 u32 bootld_size;
659 /* image */
660 u32 image_version;
661 u32 image_size;
662 /* primary image status */
663 u32 primary_status;
664 u32 secondary_present;
665
666 /* MAC address , 4 ports, 32 address per port */
667 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
668 u32 sub_sys_id;
669 u8 serial_num[32];
670
671 /* Any user defined data */
672 };
673
674 /*
675 * Flash Layout - new format.
676 */
677 struct netxen_new_user_info {
678 u8 flash_md5[16 * 64];
679 /* bootloader */
680 u32 bootld_version;
681 u32 bootld_size;
682 /* image */
683 u32 image_version;
684 u32 image_size;
685 /* primary image status */
686 u32 primary_status;
687 u32 secondary_present;
688
689 /* MAC address , 4 ports, 32 address per port */
690 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
691 u32 sub_sys_id;
692 u8 serial_num[32];
693
694 /* Any user defined data */
695 };
696
697 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
698 #define SECONDARY_IMAGE_ABSENT 0xffffffff
699 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
700 #define PRIMARY_IMAGE_BAD 0xffffffff
701
702 /* Flash memory map */
703 typedef enum {
704 NETXEN_CRBINIT_START = 0, /* Crbinit section */
705 NETXEN_BRDCFG_START = 0x4000, /* board config */
706 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
707 NETXEN_BOOTLD_START = 0x10000, /* bootld */
708 NETXEN_IMAGE_START = 0x43000, /* compressed image */
709 NETXEN_SECONDARY_START = 0x200000, /* backup images */
710 NETXEN_PXE_START = 0x3E0000, /* user defined region */
711 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
712 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
713 } netxen_flash_map_t;
714
715 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
716
717 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
718 #define NETXEN_INIT_SECTOR (0)
719 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
720 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
721 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
722 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
723 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
724 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
725 #define NETXEN_NUM_CONFIG_SECTORS (1)
726 #define PFX "NetXen: "
727 extern char netxen_nic_driver_name[];
728
729 /* Note: Make sure to not call this before adapter->port is valid */
730 #if !defined(NETXEN_DEBUG)
731 #define DPRINTK(klevel, fmt, args...) do { \
732 } while (0)
733 #else
734 #define DPRINTK(klevel, fmt, args...) do { \
735 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
736 (adapter != NULL && adapter->netdev != NULL) ? \
737 adapter->netdev->name : NULL, \
738 ## args); } while(0)
739 #endif
740
741 /* Number of status descriptors to handle per interrupt */
742 #define MAX_STATUS_HANDLE (128)
743
744 /*
745 * netxen_skb_frag{} is to contain mapping info for each SG list. This
746 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
747 */
748 struct netxen_skb_frag {
749 u64 dma;
750 ulong length;
751 };
752
753 #define _netxen_set_bits(config_word, start, bits, val) {\
754 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
755 unsigned long long __tvalue = (val); \
756 (config_word) &= ~__tmask; \
757 (config_word) |= (((__tvalue) << (start)) & __tmask); \
758 }
759
760 #define _netxen_clear_bits(config_word, start, bits) {\
761 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
762 (config_word) &= ~__tmask; \
763 }
764
765 /* Following defines are for the state of the buffers */
766 #define NETXEN_BUFFER_FREE 0
767 #define NETXEN_BUFFER_BUSY 1
768
769 /*
770 * There will be one netxen_buffer per skb packet. These will be
771 * used to save the dma info for pci_unmap_page()
772 */
773 struct netxen_cmd_buffer {
774 struct sk_buff *skb;
775 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
776 u32 frag_count;
777 };
778
779 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
780 struct netxen_rx_buffer {
781 struct list_head list;
782 struct sk_buff *skb;
783 u64 dma;
784 u16 ref_handle;
785 u16 state;
786 u32 lro_expected_frags;
787 u32 lro_current_frags;
788 u32 lro_length;
789 };
790
791 /* Board types */
792 #define NETXEN_NIC_GBE 0x01
793 #define NETXEN_NIC_XGBE 0x02
794
795 /*
796 * One hardware_context{} per adapter
797 * contains interrupt info as well shared hardware info.
798 */
799 struct netxen_hardware_context {
800 void __iomem *pci_base0;
801 void __iomem *pci_base1;
802 void __iomem *pci_base2;
803 unsigned long first_page_group_end;
804 unsigned long first_page_group_start;
805 void __iomem *db_base;
806 unsigned long db_len;
807 unsigned long pci_len0;
808
809 u8 cut_through;
810 int qdr_sn_window;
811 int ddr_mn_window;
812 unsigned long mn_win_crb;
813 unsigned long ms_win_crb;
814
815 u8 revision_id;
816 u16 board_type;
817 struct netxen_board_info boardcfg;
818 u32 linkup;
819 /* Address of cmd ring in Phantom */
820 struct cmd_desc_type0 *cmd_desc_head;
821 dma_addr_t cmd_desc_phys_addr;
822 struct netxen_adapter *adapter;
823 int pci_func;
824 };
825
826 #define RCV_RING_LRO RCV_DESC_LRO
827
828 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
829 #define ETHERNET_FCS_SIZE 4
830
831 struct netxen_adapter_stats {
832 u64 rcvdbadskb;
833 u64 xmitcalled;
834 u64 xmitedframes;
835 u64 xmitfinished;
836 u64 badskblen;
837 u64 nocmddescriptor;
838 u64 polled;
839 u64 rxdropped;
840 u64 txdropped;
841 u64 csummed;
842 u64 no_rcv;
843 u64 rxbytes;
844 u64 txbytes;
845 u64 ints;
846 };
847
848 /*
849 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
850 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
851 */
852 struct nx_host_rds_ring {
853 u32 flags;
854 u32 producer;
855 dma_addr_t phys_addr;
856 u32 crb_rcv_producer; /* reg offset */
857 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
858 u32 max_rx_desc_count;
859 u32 dma_size;
860 u32 skb_size;
861 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
862 struct list_head free_list;
863 };
864
865 /*
866 * Receive context. There is one such structure per instance of the
867 * receive processing. Any state information that is relevant to
868 * the receive, and is must be in this structure. The global data may be
869 * present elsewhere.
870 */
871 struct netxen_recv_context {
872 u32 state;
873 u16 context_id;
874 u16 virt_port;
875
876 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
877 u32 status_rx_consumer;
878 u32 crb_sts_consumer; /* reg offset */
879 dma_addr_t rcv_status_desc_phys_addr;
880 struct status_desc *rcv_status_desc_head;
881 };
882
883 /* New HW context creation */
884
885 #define NX_OS_CRB_RETRY_COUNT 4000
886 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
887 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
888
889 #define NX_CDRP_CLEAR 0x00000000
890 #define NX_CDRP_CMD_BIT 0x80000000
891
892 /*
893 * All responses must have the NX_CDRP_CMD_BIT cleared
894 * in the crb NX_CDRP_CRB_OFFSET.
895 */
896 #define NX_CDRP_FORM_RSP(rsp) (rsp)
897 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
898
899 #define NX_CDRP_RSP_OK 0x00000001
900 #define NX_CDRP_RSP_FAIL 0x00000002
901 #define NX_CDRP_RSP_TIMEOUT 0x00000003
902
903 /*
904 * All commands must have the NX_CDRP_CMD_BIT set in
905 * the crb NX_CDRP_CRB_OFFSET.
906 */
907 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
908 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
909
910 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
911 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
912 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
913 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
914 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
915 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
916 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
917 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
918 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
919 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
920 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
921 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
922 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
923 #define NX_CDRP_CMD_SET_MTU 0x00000012
924 #define NX_CDRP_CMD_MAX 0x00000013
925
926 #define NX_RCODE_SUCCESS 0
927 #define NX_RCODE_NO_HOST_MEM 1
928 #define NX_RCODE_NO_HOST_RESOURCE 2
929 #define NX_RCODE_NO_CARD_CRB 3
930 #define NX_RCODE_NO_CARD_MEM 4
931 #define NX_RCODE_NO_CARD_RESOURCE 5
932 #define NX_RCODE_INVALID_ARGS 6
933 #define NX_RCODE_INVALID_ACTION 7
934 #define NX_RCODE_INVALID_STATE 8
935 #define NX_RCODE_NOT_SUPPORTED 9
936 #define NX_RCODE_NOT_PERMITTED 10
937 #define NX_RCODE_NOT_READY 11
938 #define NX_RCODE_DOES_NOT_EXIST 12
939 #define NX_RCODE_ALREADY_EXISTS 13
940 #define NX_RCODE_BAD_SIGNATURE 14
941 #define NX_RCODE_CMD_NOT_IMPL 15
942 #define NX_RCODE_CMD_INVALID 16
943 #define NX_RCODE_TIMEOUT 17
944 #define NX_RCODE_CMD_FAILED 18
945 #define NX_RCODE_MAX_EXCEEDED 19
946 #define NX_RCODE_MAX 20
947
948 #define NX_DESTROY_CTX_RESET 0
949 #define NX_DESTROY_CTX_D3_RESET 1
950 #define NX_DESTROY_CTX_MAX 2
951
952 /*
953 * Capabilities
954 */
955 #define NX_CAP_BIT(class, bit) (1 << bit)
956 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
957 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
958 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
959 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
960 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
961 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
962 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
963 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
964 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
965
966 /*
967 * Context state
968 */
969 #define NX_HOST_CTX_STATE_FREED 0
970 #define NX_HOST_CTX_STATE_ALLOCATED 1
971 #define NX_HOST_CTX_STATE_ACTIVE 2
972 #define NX_HOST_CTX_STATE_DISABLED 3
973 #define NX_HOST_CTX_STATE_QUIESCED 4
974 #define NX_HOST_CTX_STATE_MAX 5
975
976 /*
977 * Rx context
978 */
979
980 typedef struct {
981 __le64 host_phys_addr; /* Ring base addr */
982 __le32 ring_size; /* Ring entries */
983 __le16 msi_index;
984 __le16 rsvd; /* Padding */
985 } nx_hostrq_sds_ring_t;
986
987 typedef struct {
988 __le64 host_phys_addr; /* Ring base addr */
989 __le64 buff_size; /* Packet buffer size */
990 __le32 ring_size; /* Ring entries */
991 __le32 ring_kind; /* Class of ring */
992 } nx_hostrq_rds_ring_t;
993
994 typedef struct {
995 __le64 host_rsp_dma_addr; /* Response dma'd here */
996 __le32 capabilities[4]; /* Flag bit vector */
997 __le32 host_int_crb_mode; /* Interrupt crb usage */
998 __le32 host_rds_crb_mode; /* RDS crb usage */
999 /* These ring offsets are relative to data[0] below */
1000 __le32 rds_ring_offset; /* Offset to RDS config */
1001 __le32 sds_ring_offset; /* Offset to SDS config */
1002 __le16 num_rds_rings; /* Count of RDS rings */
1003 __le16 num_sds_rings; /* Count of SDS rings */
1004 __le16 rsvd1; /* Padding */
1005 __le16 rsvd2; /* Padding */
1006 u8 reserved[128]; /* reserve space for future expansion*/
1007 /* MUST BE 64-bit aligned.
1008 The following is packed:
1009 - N hostrq_rds_rings
1010 - N hostrq_sds_rings */
1011 char data[0];
1012 } nx_hostrq_rx_ctx_t;
1013
1014 typedef struct {
1015 __le32 host_producer_crb; /* Crb to use */
1016 __le32 rsvd1; /* Padding */
1017 } nx_cardrsp_rds_ring_t;
1018
1019 typedef struct {
1020 __le32 host_consumer_crb; /* Crb to use */
1021 __le32 interrupt_crb; /* Crb to use */
1022 } nx_cardrsp_sds_ring_t;
1023
1024 typedef struct {
1025 /* These ring offsets are relative to data[0] below */
1026 __le32 rds_ring_offset; /* Offset to RDS config */
1027 __le32 sds_ring_offset; /* Offset to SDS config */
1028 __le32 host_ctx_state; /* Starting State */
1029 __le32 num_fn_per_port; /* How many PCI fn share the port */
1030 __le16 num_rds_rings; /* Count of RDS rings */
1031 __le16 num_sds_rings; /* Count of SDS rings */
1032 __le16 context_id; /* Handle for context */
1033 u8 phys_port; /* Physical id of port */
1034 u8 virt_port; /* Virtual/Logical id of port */
1035 u8 reserved[128]; /* save space for future expansion */
1036 /* MUST BE 64-bit aligned.
1037 The following is packed:
1038 - N cardrsp_rds_rings
1039 - N cardrs_sds_rings */
1040 char data[0];
1041 } nx_cardrsp_rx_ctx_t;
1042
1043 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1044 (sizeof(HOSTRQ_RX) + \
1045 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1046 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1047
1048 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1049 (sizeof(CARDRSP_RX) + \
1050 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1051 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1052
1053 /*
1054 * Tx context
1055 */
1056
1057 typedef struct {
1058 __le64 host_phys_addr; /* Ring base addr */
1059 __le32 ring_size; /* Ring entries */
1060 __le32 rsvd; /* Padding */
1061 } nx_hostrq_cds_ring_t;
1062
1063 typedef struct {
1064 __le64 host_rsp_dma_addr; /* Response dma'd here */
1065 __le64 cmd_cons_dma_addr; /* */
1066 __le64 dummy_dma_addr; /* */
1067 __le32 capabilities[4]; /* Flag bit vector */
1068 __le32 host_int_crb_mode; /* Interrupt crb usage */
1069 __le32 rsvd1; /* Padding */
1070 __le16 rsvd2; /* Padding */
1071 __le16 interrupt_ctl;
1072 __le16 msi_index;
1073 __le16 rsvd3; /* Padding */
1074 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1075 u8 reserved[128]; /* future expansion */
1076 } nx_hostrq_tx_ctx_t;
1077
1078 typedef struct {
1079 __le32 host_producer_crb; /* Crb to use */
1080 __le32 interrupt_crb; /* Crb to use */
1081 } nx_cardrsp_cds_ring_t;
1082
1083 typedef struct {
1084 __le32 host_ctx_state; /* Starting state */
1085 __le16 context_id; /* Handle for context */
1086 u8 phys_port; /* Physical id of port */
1087 u8 virt_port; /* Virtual/Logical id of port */
1088 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1089 u8 reserved[128]; /* future expansion */
1090 } nx_cardrsp_tx_ctx_t;
1091
1092 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1093 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1094
1095 /* CRB */
1096
1097 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1098 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1099 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1100 #define NX_HOST_RDS_CRB_MODE_MAX 3
1101
1102 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1103 #define NX_HOST_INT_CRB_MODE_SHARED 1
1104 #define NX_HOST_INT_CRB_MODE_NORX 2
1105 #define NX_HOST_INT_CRB_MODE_NOTX 3
1106 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1107
1108
1109 /* MAC */
1110
1111 #define MC_COUNT_P2 16
1112 #define MC_COUNT_P3 38
1113
1114 #define NETXEN_MAC_NOOP 0
1115 #define NETXEN_MAC_ADD 1
1116 #define NETXEN_MAC_DEL 2
1117
1118 typedef struct nx_mac_list_s {
1119 struct nx_mac_list_s *next;
1120 uint8_t mac_addr[MAX_ADDR_LEN];
1121 } nx_mac_list_t;
1122
1123 /*
1124 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1125 * adjusted based on configured MTU.
1126 */
1127 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1128 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1129 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1130 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1131
1132 #define NETXEN_NIC_INTR_DEFAULT 0x04
1133
1134 typedef union {
1135 struct {
1136 uint16_t rx_packets;
1137 uint16_t rx_time_us;
1138 uint16_t tx_packets;
1139 uint16_t tx_time_us;
1140 } data;
1141 uint64_t word;
1142 } nx_nic_intr_coalesce_data_t;
1143
1144 typedef struct {
1145 uint16_t stats_time_us;
1146 uint16_t rate_sample_time;
1147 uint16_t flags;
1148 uint16_t rsvd_1;
1149 uint32_t low_threshold;
1150 uint32_t high_threshold;
1151 nx_nic_intr_coalesce_data_t normal;
1152 nx_nic_intr_coalesce_data_t low;
1153 nx_nic_intr_coalesce_data_t high;
1154 nx_nic_intr_coalesce_data_t irq;
1155 } nx_nic_intr_coalesce_t;
1156
1157 #define NX_HOST_REQUEST 0x13
1158 #define NX_NIC_REQUEST 0x14
1159
1160 #define NX_MAC_EVENT 0x1
1161
1162 enum {
1163 NX_NIC_H2C_OPCODE_START = 0,
1164 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1165 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1166 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1167 NX_NIC_H2C_OPCODE_CONFIG_LED,
1168 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1169 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1170 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1171 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1172 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1173 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1174 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1175 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1176 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1177 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1178 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1179 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1180 NX_NIC_H2C_OPCODE_LAST
1181 };
1182
1183 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1184 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1185 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1186
1187 typedef struct {
1188 __le64 qhdr;
1189 __le64 req_hdr;
1190 __le64 words[6];
1191 } nx_nic_req_t;
1192
1193 typedef struct {
1194 u8 op;
1195 u8 tag;
1196 u8 mac_addr[6];
1197 } nx_mac_req_t;
1198
1199 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1200
1201 #define NETXEN_NIC_MSI_ENABLED 0x02
1202 #define NETXEN_NIC_MSIX_ENABLED 0x04
1203 #define NETXEN_IS_MSI_FAMILY(adapter) \
1204 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1205
1206 #define MSIX_ENTRIES_PER_ADAPTER 1
1207 #define NETXEN_MSIX_TBL_SPACE 8192
1208 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1209
1210 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1211
1212 #define NETXEN_NETDEV_WEIGHT 120
1213 #define NETXEN_ADAPTER_UP_MAGIC 777
1214 #define NETXEN_NIC_PEG_TUNE 0
1215
1216 struct netxen_dummy_dma {
1217 void *addr;
1218 dma_addr_t phys_addr;
1219 };
1220
1221 struct netxen_adapter {
1222 struct netxen_hardware_context ahw;
1223
1224 struct net_device *netdev;
1225 struct pci_dev *pdev;
1226 int pci_using_dac;
1227 struct napi_struct napi;
1228 struct net_device_stats net_stats;
1229 int mtu;
1230 int portnum;
1231 u8 physical_port;
1232 u16 tx_context_id;
1233
1234 uint8_t mc_enabled;
1235 uint8_t max_mc_count;
1236 nx_mac_list_t *mac_list;
1237
1238 struct netxen_legacy_intr_set legacy_intr;
1239 u32 crb_intr_mask;
1240
1241 struct work_struct watchdog_task;
1242 struct timer_list watchdog_timer;
1243 struct work_struct tx_timeout_task;
1244
1245 u32 curr_window;
1246 u32 crb_win;
1247 rwlock_t adapter_lock;
1248
1249 uint64_t dma_mask;
1250
1251 u32 cmd_producer;
1252 __le32 *cmd_consumer;
1253 u32 last_cmd_consumer;
1254 u32 crb_addr_cmd_producer;
1255 u32 crb_addr_cmd_consumer;
1256
1257 u32 max_tx_desc_count;
1258 u32 max_rx_desc_count;
1259 u32 max_jumbo_rx_desc_count;
1260 u32 max_lro_rx_desc_count;
1261
1262 int max_rds_rings;
1263
1264 u32 flags;
1265 u32 irq;
1266 int driver_mismatch;
1267 u32 temp;
1268
1269 u32 fw_major;
1270
1271 u8 msix_supported;
1272 u8 max_possible_rss_rings;
1273 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1274
1275 struct netxen_adapter_stats stats;
1276
1277 u16 link_speed;
1278 u16 link_duplex;
1279 u16 state;
1280 u16 link_autoneg;
1281 int rx_csum;
1282 int status;
1283
1284 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1285
1286 /*
1287 * Receive instances. These can be either one per port,
1288 * or one per peg, etc.
1289 */
1290 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
1291
1292 int is_up;
1293 struct netxen_dummy_dma dummy_dma;
1294 nx_nic_intr_coalesce_t coal;
1295
1296 /* Context interface shared between card and host */
1297 struct netxen_ring_ctx *ctx_desc;
1298 dma_addr_t ctx_desc_phys_addr;
1299 int intr_scheme;
1300 int msi_mode;
1301 int (*enable_phy_interrupts) (struct netxen_adapter *);
1302 int (*disable_phy_interrupts) (struct netxen_adapter *);
1303 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1304 int (*set_mtu) (struct netxen_adapter *, int);
1305 int (*set_promisc) (struct netxen_adapter *, u32);
1306 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1307 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1308 int (*init_port) (struct netxen_adapter *, int);
1309 int (*stop_port) (struct netxen_adapter *);
1310
1311 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1312 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1313 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1314 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1315 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1316 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1317 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1318 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1319 unsigned long (*pci_set_window)(struct netxen_adapter *,
1320 unsigned long long);
1321 }; /* netxen_adapter structure */
1322
1323 /*
1324 * NetXen dma watchdog control structure
1325 *
1326 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1327 * Bit 1 : disable_request => 1 req disable dma watchdog
1328 * Bit 2 : enable_request => 1 req enable dma watchdog
1329 * Bit 3-31 : unused
1330 */
1331
1332 #define netxen_set_dma_watchdog_disable_req(config_word) \
1333 _netxen_set_bits(config_word, 1, 1, 1)
1334 #define netxen_set_dma_watchdog_enable_req(config_word) \
1335 _netxen_set_bits(config_word, 2, 1, 1)
1336 #define netxen_get_dma_watchdog_enabled(config_word) \
1337 ((config_word) & 0x1)
1338 #define netxen_get_dma_watchdog_disabled(config_word) \
1339 (((config_word) >> 1) & 0x1)
1340
1341 /* Max number of xmit producer threads that can run simultaneously */
1342 #define MAX_XMIT_PRODUCERS 16
1343
1344 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1345 ((adapter)->ahw.pci_base0 + (off))
1346 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1347 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1348 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1349 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1350
pci_base_offset(struct netxen_adapter * adapter,unsigned long off)1351 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1352 unsigned long off)
1353 {
1354 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1355 return (adapter->ahw.pci_base0 + off);
1356 } else if ((off < SECOND_PAGE_GROUP_END) &&
1357 (off >= SECOND_PAGE_GROUP_START)) {
1358 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1359 } else if ((off < THIRD_PAGE_GROUP_END) &&
1360 (off >= THIRD_PAGE_GROUP_START)) {
1361 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1362 }
1363 return NULL;
1364 }
1365
pci_base(struct netxen_adapter * adapter,unsigned long off)1366 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1367 unsigned long off)
1368 {
1369 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1370 return adapter->ahw.pci_base0;
1371 } else if ((off < SECOND_PAGE_GROUP_END) &&
1372 (off >= SECOND_PAGE_GROUP_START)) {
1373 return adapter->ahw.pci_base1;
1374 } else if ((off < THIRD_PAGE_GROUP_END) &&
1375 (off >= THIRD_PAGE_GROUP_START)) {
1376 return adapter->ahw.pci_base2;
1377 }
1378 return NULL;
1379 }
1380
1381 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1382 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1383 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1384 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1385 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1386 __u32 * readval);
1387 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1388 long reg, __u32 val);
1389
1390 /* Functions available from netxen_nic_hw.c */
1391 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1392 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1393 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1394 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1395 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1396 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1397 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1398 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1399
1400 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1401
1402 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1403 ulong off, void *data, int len);
1404 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1405 ulong off, void *data, int len);
1406 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1407 u64 off, void *data, int size);
1408 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1409 u64 off, void *data, int size);
1410 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1411 u64 off, u32 data);
1412 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1413 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1414 u64 off, u32 data);
1415 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1416 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1417 unsigned long long addr);
1418 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1419 u32 wndw);
1420
1421 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1422 ulong off, void *data, int len);
1423 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1424 ulong off, void *data, int len);
1425 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1426 u64 off, void *data, int size);
1427 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1428 u64 off, void *data, int size);
1429 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1430 unsigned long off, int data);
1431 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1432 u64 off, u32 data);
1433 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1434 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1435 u64 off, u32 data);
1436 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1437 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1438 unsigned long long addr);
1439
1440 /* Functions from netxen_nic_init.c */
1441 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1442 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1443 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1444 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1445 int netxen_load_firmware(struct netxen_adapter *adapter);
1446 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1447
1448 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1449 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1450 u8 *bytes, size_t size);
1451 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1452 u8 *bytes, size_t size);
1453 int netxen_flash_unlock(struct netxen_adapter *adapter);
1454 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1455 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1456 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1457 void netxen_halt_pegs(struct netxen_adapter *adapter);
1458
1459 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1460
1461 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1462 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1463
1464 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1465 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1466
1467 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1468 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1469
1470 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1471 int netxen_init_firmware(struct netxen_adapter *adapter);
1472 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1473 void netxen_watchdog_task(struct work_struct *work);
1474 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1475 u32 ringid);
1476 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1477 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1478 void netxen_p2_nic_set_multi(struct net_device *netdev);
1479 void netxen_p3_nic_set_multi(struct net_device *netdev);
1480 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1481 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1482 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1483
1484 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1485 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1486
1487 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1488 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1489
1490 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1491 uint32_t crb_producer);
1492
1493 /*
1494 * NetXen Board information
1495 */
1496
1497 #define NETXEN_MAX_SHORT_NAME 32
1498 struct netxen_brdinfo {
1499 netxen_brdtype_t brdtype; /* type of board */
1500 long ports; /* max no of physical ports */
1501 char short_name[NETXEN_MAX_SHORT_NAME];
1502 };
1503
1504 static const struct netxen_brdinfo netxen_boards[] = {
1505 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1506 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1507 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1508 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1509 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1510 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1511 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1512 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1513 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1514 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1515 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1516 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1517 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1518 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1519 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1520 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1521 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1522 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1523 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1524 };
1525
1526 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1527
get_brd_name_by_type(u32 type,char * name)1528 static inline void get_brd_name_by_type(u32 type, char *name)
1529 {
1530 int i, found = 0;
1531 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1532 if (netxen_boards[i].brdtype == type) {
1533 strcpy(name, netxen_boards[i].short_name);
1534 found = 1;
1535 break;
1536 }
1537
1538 }
1539 if (!found)
1540 name = "Unknown";
1541 }
1542
1543 static inline int
dma_watchdog_shutdown_request(struct netxen_adapter * adapter)1544 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1545 {
1546 u32 ctrl;
1547
1548 /* check if already inactive */
1549 if (adapter->hw_read_wx(adapter,
1550 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1551 printk(KERN_ERR "failed to read dma watchdog status\n");
1552
1553 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1554 return 1;
1555
1556 /* Send the disable request */
1557 netxen_set_dma_watchdog_disable_req(ctrl);
1558 netxen_crb_writelit_adapter(adapter,
1559 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1560
1561 return 0;
1562 }
1563
1564 static inline int
dma_watchdog_shutdown_poll_result(struct netxen_adapter * adapter)1565 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1566 {
1567 u32 ctrl;
1568
1569 if (adapter->hw_read_wx(adapter,
1570 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1571 printk(KERN_ERR "failed to read dma watchdog status\n");
1572
1573 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1574 }
1575
1576 static inline int
dma_watchdog_wakeup(struct netxen_adapter * adapter)1577 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1578 {
1579 u32 ctrl;
1580
1581 if (adapter->hw_read_wx(adapter,
1582 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1583 printk(KERN_ERR "failed to read dma watchdog status\n");
1584
1585 if (netxen_get_dma_watchdog_enabled(ctrl))
1586 return 1;
1587
1588 /* send the wakeup request */
1589 netxen_set_dma_watchdog_enable_req(ctrl);
1590
1591 netxen_crb_writelit_adapter(adapter,
1592 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1593
1594 return 0;
1595 }
1596
1597
1598 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1599 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1600 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1601 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1602 int *valp);
1603
1604 extern struct ethtool_ops netxen_nic_ethtool_ops;
1605
1606 #endif /* __NETXEN_NIC_H_ */
1607