Searched refs:pins (Results 1 – 22 of 22) sorted by relevance
386 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) { in get_pins() argument387 unsigned int b0 = readb(pins); in get_pins()389 if (b0 == 0x2E && readb(pins+1) == 0x41) { in get_pins()390 unsigned int pins_len = readb(pins+2); in get_pins()393 unsigned char* dst = bd->pins; in get_pins()403 cksum += *dst++ = readb(pins+i); in get_pins()409 } else if (b0 == 0x40 && readb(pins+1) == 0x00) { in get_pins()411 unsigned char* dst = bd->pins; in get_pins()416 *dst++ = readb(pins+i); in get_pins()528 switch (bd->pins[22]) { in parse_pins1()[all …]
341 unsigned char pins[128]; member
70 pin = pdata->pins[i]; in gpio_mouse_probe()145 pin = pdata->pins[i]; in gpio_mouse_probe()163 pin = pdata->pins[i]; in gpio_mouse_remove()
142 qe_pin_set_dedicated(fhci->pins[PIN_USBOE]); in fhci_io_port_generate_reset()143 qe_pin_set_dedicated(fhci->pins[PIN_USBTP]); in fhci_io_port_generate_reset()144 qe_pin_set_dedicated(fhci->pins[PIN_USBTN]); in fhci_io_port_generate_reset()
671 fhci->pins[j] = qe_pin_request(ofdev->node, j); in of_fhci_probe()672 if (IS_ERR(fhci->pins[j])) { in of_fhci_probe()673 ret = PTR_ERR(fhci->pins[j]); in of_fhci_probe()765 qe_pin_free(fhci->pins[j]); in of_fhci_probe()796 qe_pin_free(fhci->pins[j]); in fhci_remove()
265 struct qe_pin *pins[NUM_PINS]; member
174 1..17 : directly connected to any of these pins on the DB25 plug189 1..17 : directly connected to any of these pins on the DB25 plug204 1..17 : directly connected to any of these pins on the DB25 plug219 1..17 : directly connected to any of these pins on the DB25 plug234 1..17 : directly connected to any of these pins on the DB25 plug249 1..17 : directly connected to any of these pins on the DB25 plug
12 using Matrox's G400 GPIO pins.56 GPIO pins. This driver uses the GPIO API to control the wire.
51 pins, output pins, and irqs.240 Say yes here if you want to include support GPIO for pins on
83 With a few GPIO pins, your system can bitbang the SPI protocol.84 Select this to get SPI support through I/O pins (GPIO, parallel198 where the board is using non hardware connected pins.
99 drive the relevant pins.
297 to GPIO pins of various CPUs (and some other chips).300 directly to such GPIO pins. Your board-specific
304 .pins = {319 .pins = {
152 The BT8xx frame grabber chip has 24 GPIO pins than can be abused
62 ixp4xx gpio pins. This is used by the LinkSys NSLU2.
19 are connected to an ADB port. ADB devices tend to have 4 pins.
676 tristate "NatSemi SCx200 I2C using GPIO pins (DEPRECATED)"680 Enable the use of two GPIO pins of a SCx200 processor as an I2C bus.
98 * Reads the actual state of the SCSI bus pins313 bit DUAL_EDGE_ERROR 0x01 /* Invalid pins for Dual Edge phase */
995 Give userspace access to the GPIO pins on the National1006 Give userspace access to the GPIO pins on the National1027 Give userspace access to the GPIO pins on the AMD CS5535 and
309 to plug a specific 5 pins FIR IrDA dongle in the specific
116 * Reads the actual state of the SCSI bus pins
456 pins are configured.