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Searched refs:pll (Results 1 – 25 of 40) sorted by relevance

12

/drivers/video/aty/
Dmach64_ct.c17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
129 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
135 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
141 if (pll->xres != 0) { in aty_dsp_gt()
[all …]
Dmach64_gx.c80 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
123 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
153 pll->ibm514.m = RGB514_clocks[i].m; in aty_var_to_pll_514()
154 pll->ibm514.n = RGB514_clocks[i].n; in aty_var_to_pll_514()
161 const union aty_pll *pll) in aty_pll_514_to_var() argument
166 df = pll->ibm514.m >> 6; in aty_pll_514_to_var()
167 vco_div_count = pll->ibm514.m & 0x3f; in aty_pll_514_to_var()
168 ref_div_count = pll->ibm514.n; in aty_pll_514_to_var()
175 const union aty_pll *pll) in aty_set_pll_514() argument
185 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ in aty_set_pll_514()
[all …]
Dradeon_base.c439 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
443 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
447 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
583 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
584 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
585 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
586 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
604 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
605 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
606 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
[all …]
Datyfb.h136 union aty_pll pll; member
300 const union aty_pll * pll, u32 bpp, u32 accel);
315 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
316 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
317 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
318 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
319 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
320 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
332 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
Datyfb_base.c307 static int pll; variable
370 int pll, mclk, xclk, ecp_max; member
443 par->pll_limits.pll_max = aty_chips[i].pll; in correct_chipset()
565 par->pll.ct.xres = 0; in atyfb_get_pixclock()
569 par->pll.ct.xres = var->xres; in atyfb_get_pixclock()
1275 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll))) in atyfb_set_par()
1293 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags); in atyfb_set_par()
1294 par->pll_ops->set_pll(info, &par->pll); in atyfb_set_par()
1298 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll)); in atyfb_set_par()
1475 union aty_pll pll; in atyfb_check_var() local
[all …]
Daty128fb.c402 struct aty128_pll pll; member
1285 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par) in aty128_set_pll() argument
1306 div3 |= pll->feedback_divider; in aty128_set_pll()
1308 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1324 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, in aty128_var_to_pll() argument
1346 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1358 pll->feedback_divider = round_div(n, d); in aty128_var_to_pll()
1359 pll->vclk = vclk; in aty128_var_to_pll()
1362 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
1363 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
/drivers/video/matrox/
Dg450_pll.c33 return (ACCESS_FBINFO(features).pll.ref_freq * n + (m >> 1)) / m; in g450_mnp2vco()
93 …n = ((tvco * (m+1) + ACCESS_FBINFO(features).pll.ref_freq) / (ACCESS_FBINFO(features).pll.ref_freq… in g450_nextpll()
127 static inline unsigned int g450_setpll(CPMINFO unsigned int mnp, unsigned int pll) { in g450_setpll() argument
128 switch (pll) { in g450_setpll()
162 static inline unsigned int g450_cmppll(CPMINFO unsigned int mnp, unsigned int pll) { in g450_cmppll() argument
167 switch (pll) { in g450_cmppll()
214 static int g450_testpll(CPMINFO unsigned int mnp, unsigned int pll) { in g450_testpll() argument
215 return g450_isplllocked(PMINFO g450_setpll(PMINFO mnp, pll)); in g450_testpll()
218 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { in updatehwstate_clk() argument
219 switch (pll) { in updatehwstate_clk()
[all …]
Dmatroxfb_misc.c126 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f… in matroxfb_PLL_calcclock() argument
130 unsigned int fxtal = pll->ref_freq; in matroxfb_PLL_calcclock()
139 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); in matroxfb_PLL_calcclock()
140 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); in matroxfb_PLL_calcclock()
142 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); in matroxfb_PLL_calcclock()
143 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); in matroxfb_PLL_calcclock()
144 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); in matroxfb_PLL_calcclock()
145 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); in matroxfb_PLL_calcclock()
146 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); in matroxfb_PLL_calcclock()
149 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_calcclock()
[all …]
Dmatroxfb_DAC1064.c172 } else if (ACCESS_FBINFO(crtc2).pixclock == ACCESS_FBINFO(features).pll.ref_freq) { in g450_set_plls()
571 ACCESS_FBINFO(features.pll.vco_freq_min) = 62000; in MGA1064_ramdac_init()
572 ACCESS_FBINFO(features.pll.ref_freq) = 14318; in MGA1064_ramdac_init()
573 ACCESS_FBINFO(features.pll.feed_div_min) = 100; in MGA1064_ramdac_init()
574 ACCESS_FBINFO(features.pll.feed_div_max) = 127; in MGA1064_ramdac_init()
575 ACCESS_FBINFO(features.pll.in_div_min) = 1; in MGA1064_ramdac_init()
576 ACCESS_FBINFO(features.pll.in_div_max) = 31; in MGA1064_ramdac_init()
577 ACCESS_FBINFO(features.pll.post_shift_max) = 3; in MGA1064_ramdac_init()
702 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.video), M_VIDEO_PLL); in g450_mclk_init()
712 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.system), M_SYSTEM_PLL); in g450_mclk_init()
[all …]
Dg450_pll.h6 int matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll);
8 void matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll);
Dmatroxfb_misc.h7 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f…
11 return matroxfb_PLL_calcclock(&ACCESS_FBINFO(features.pll), freq, fmax, in, feed, post); in PLL_calcclock()
Dmatroxfb_Ti3026.c539 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000; in ti3026_ramdac_init()
540 ACCESS_FBINFO(features.pll.ref_freq) = 114545; in ti3026_ramdac_init()
541 ACCESS_FBINFO(features.pll.feed_div_min) = 2; in ti3026_ramdac_init()
542 ACCESS_FBINFO(features.pll.feed_div_max) = 24; in ti3026_ramdac_init()
543 ACCESS_FBINFO(features.pll.in_div_min) = 2; in ti3026_ramdac_init()
544 ACCESS_FBINFO(features.pll.in_div_max) = 63; in ti3026_ramdac_init()
545 ACCESS_FBINFO(features.pll.post_shift_max) = 3; in ti3026_ramdac_init()
Dmatroxfb_maven.c208 static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, in matroxfb_PLL_mavenclock() argument
215 unsigned int fmin = pll->vco_freq_min / ctl->den; in matroxfb_PLL_mavenclock()
225 fmax = pll->vco_freq_max / ctl->den; in matroxfb_PLL_mavenclock()
229 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_mavenclock()
240 for (m = pll->in_div_min; m <= pll->in_div_max; m++) { in matroxfb_PLL_mavenclock()
246 if (n < pll->feed_div_min) in matroxfb_PLL_mavenclock()
248 if (n > pll->feed_div_max) in matroxfb_PLL_mavenclock()
/drivers/media/video/bt8xx/
Dbttv-cards.c90 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
114 module_param_array(pll, int, NULL, 0444);
126 MODULE_PARM_DESC(pll,"specify installed crystal (0=none, 28=28 MHz, 35=35 MHz)");
372 .pll = PLL_28,
450 .pll = PLL_28,
465 .pll = PLL_28,
481 .pll = PLL_28,
528 .pll = PLL_28,
546 .pll = PLL_28,
580 .pll = PLL_28,
[all …]
Dbttv-driver.c993 if (!btv->pll.pll_crystal) in set_pll()
996 if (btv->pll.pll_ofreq == btv->pll.pll_current) { in set_pll()
1001 if (btv->pll.pll_ifreq == btv->pll.pll_ofreq) { in set_pll()
1003 if (btv->pll.pll_current == 0) in set_pll()
1006 btv->c.nr,btv->pll.pll_ifreq); in set_pll()
1009 btv->pll.pll_current = 0; in set_pll()
1014 btv->pll.pll_ifreq, btv->pll.pll_ofreq); in set_pll()
1015 set_pll_freq(btv, btv->pll.pll_ifreq, btv->pll.pll_ofreq); in set_pll()
1026 btv->pll.pll_current = btv->pll.pll_ofreq; in set_pll()
1031 btv->pll.pll_current = -1; in set_pll()
[all …]
/drivers/char/
Dgenrtc.c268 struct rtc_pll_info pll; in gen_rtc_ioctl() local
274 if (get_rtc_pll(&pll)) in gen_rtc_ioctl()
277 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; in gen_rtc_ioctl()
282 if (copy_from_user(&pll, argp, sizeof(pll))) in gen_rtc_ioctl()
284 return set_rtc_pll(&pll); in gen_rtc_ioctl()
381 struct rtc_pll_info pll; in gen_rtc_proc_output() local
431 if (!get_rtc_pll(&pll)) in gen_rtc_proc_output()
439 pll.pll_value, in gen_rtc_proc_output()
440 pll.pll_max, in gen_rtc_proc_output()
441 pll.pll_min, in gen_rtc_proc_output()
[all …]
/drivers/video/nvidia/
Dnv_hw.c144 unsigned int pll, N, M, MB, NB, P; in nvGetClocks() local
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
148 P = (pll >> 16) & 0x07; in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
150 M = pll & 0xFF; in nvGetClocks()
151 N = (pll >> 8) & 0xFF; in nvGetClocks()
157 MB = (pll >> 16) & 0xFF; in nvGetClocks()
158 NB = (pll >> 24) & 0xFF; in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
163 P = (pll >> 16) & 0x07; in nvGetClocks()
[all …]
/drivers/video/
Dsvgalib.c382 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) in svga_compute_pll() argument
389 ar = pll->r_max; in svga_compute_pll()
399 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { in svga_compute_pll()
405 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) in svga_compute_pll()
413 am = pll->m_min; in svga_compute_pll()
414 an = pll->n_min; in svga_compute_pll()
416 while ((am <= pll->m_max) && (an <= pll->n_max)) { in svga_compute_pll()
417 f_current = (pll->f_base * am) / an; in svga_compute_pll()
433 f_current = (pll->f_base * *m) / *n; in svga_compute_pll()
Dw100fb.c1066 static int w100_pll_adjust(struct w100_pll_info *pll) in w100_pll_adjust() argument
1090 if (tf80 >= (pll->tfgoal)) { in w100_pll_adjust()
1096 if (tf20 <= (pll->tfgoal)) in w100_pll_adjust()
1124 static int w100_pll_calibration(struct w100_pll_info *pll) in w100_pll_calibration() argument
1128 status = w100_pll_adjust(pll); in w100_pll_calibration()
1153 static int w100_pll_set_clk(struct w100_pll_info *pll) in w100_pll_set_clk() argument
1168 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; in w100_pll_set_clk()
1169 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; in w100_pll_set_clk()
1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; in w100_pll_set_clk()
1171 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time; in w100_pll_set_clk()
[all …]
/drivers/video/intelfb/
Dintelfbhw.c637 struct pll_min_max *pll = &plls[index]; in calc_vclock() local
642 vco = pll->ref_clk * m / n; in calc_vclock()
853 struct pll_min_max *pll = &plls[index]; in splitm() local
856 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { in splitm()
857 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { in splitm()
874 struct pll_min_max *pll = &plls[index]; in splitp() local
891 if (p % 4 == 0 && p1 < pll->min_p1) { in splitp()
895 if (p1 < pll->min_p1 || p1 > pll->max_p1 || in splitp()
913 struct pll_min_max *pll = &plls[index]; in calc_pll_params() local
921 div_max = pll->max_vco / clock; in calc_pll_params()
[all …]
/drivers/video/riva/
Driva_hw.c620 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
623 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv3UpdateArbitrationSettings()
809 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
812 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
814 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
815 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
1072 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1074 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
[all …]
/drivers/media/video/cx18/
Dcx18-av-core.c272 int fin, fsc, pll; in cx18_av_std_setup() local
274 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; in cx18_av_std_setup()
275 pll /= pll_post; in cx18_av_std_setup()
277 pll / 1000000, pll % 1000000); in cx18_av_std_setup()
279 pll / 8000000, (pll / 8) % 1000000); in cx18_av_std_setup()
281 fin = ((u64)src_decimation * pll) >> 12; in cx18_av_std_setup()
285 fsc = (((u64)sc) * pll) >> 24L; in cx18_av_std_setup()
/drivers/media/video/cx25840/
Dcx25840-core.c429 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L; in cx25840_std_setup() local
431 pll /= pll_post; in cx25840_std_setup()
433 pll / 1000000, pll % 1000000); in cx25840_std_setup()
435 pll / 8000000, (pll / 8) % 1000000); in cx25840_std_setup()
437 fin = ((u64)src_decimation * pll) >> 12; in cx25840_std_setup()
442 fsc = (((u64)sc) * pll) >> 24L; in cx25840_std_setup()
/drivers/net/wireless/ath9k/
Dhw.c988 u32 pll; in ath9k_hw_init_pll() local
992 pll = 0x1450; in ath9k_hw_init_pll()
994 pll = 0x1458; in ath9k_hw_init_pll()
997 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ath9k_hw_init_pll()
1000 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ath9k_hw_init_pll()
1002 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ath9k_hw_init_pll()
1005 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); in ath9k_hw_init_pll()
1011 pll = 0x2850; in ath9k_hw_init_pll()
1013 pll = 0x142c; in ath9k_hw_init_pll()
1016 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); in ath9k_hw_init_pll()
[all …]
/drivers/media/video/cx88/
Dcx88-core.c760 u64 pll; in set_pll() local
769 pll = ofreq * 8 * prescale * (u64)(1 << 20); in set_pll()
770 do_div(pll,xtal); in set_pll()
771 reg = (pll & 0x3ffffff) | (pre[prescale] << 26); in set_pll()

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