| /drivers/gpu/drm/savage/ |
| D | savage_state.c | 283 unsigned int prim = cmd_header->prim.prim; in savage_dispatch_dma_prim() local
284 unsigned int skip = cmd_header->prim.skip; in savage_dispatch_dma_prim()
285 unsigned int n = cmd_header->prim.count; in savage_dispatch_dma_prim()
286 unsigned int start = cmd_header->prim.start; in savage_dispatch_dma_prim()
298 switch (prim) { in savage_dispatch_dma_prim()
301 prim = SAVAGE_PRIM_TRILIST; in savage_dispatch_dma_prim()
319 DRM_ERROR("invalid primitive type %u\n", prim); in savage_dispatch_dma_prim()
371 prim <<= 25; in savage_dispatch_dma_prim()
383 BCI_DRAW_INDICES_S3D(count, prim, start + 2); in savage_dispatch_dma_prim()
393 BCI_DRAW_INDICES_S3D(count, prim, start); in savage_dispatch_dma_prim()
[all …]
|
| /drivers/gpu/drm/mga/ |
| D | mga_drv.h | 78 drm_mga_primary_buffer_t prim; member
250 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
253 } else if ( dev_priv->prim.space < \
254 dev_priv->prim.high_mark ) { \
264 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
280 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
289 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
291 prim = dev_priv->prim.start; \
292 write = dev_priv->prim.tail; \
299 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
[all …]
|
| D | mga_dma.c | 80 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
163 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_wrap_start()
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_wrap_end()
897 dev_priv->prim.status = (u32 *) dev_priv->status->handle; in mga_do_init_dma()
905 …MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap,… in mga_do_init_dma()
909 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; in mga_do_init_dma()
910 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle in mga_do_init_dma()
912 dev_priv->prim.size = dev_priv->primary->size; in mga_do_init_dma()
914 dev_priv->prim.tail = 0; in mga_do_init_dma()
[all …]
|
| D | mga_state.c | 582 sarea_priv->last_frame.head = dev_priv->prim.tail; in mga_dma_dispatch_swap()
583 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; in mga_dma_dispatch_swap()
|
| /drivers/gpu/drm/radeon/ |
| D | radeon_state.c | 1495 unsigned int prim; member
1504 drm_radeon_tcl_prim_t * prim) in radeon_cp_dispatch_vertex() argument
1509 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; in radeon_cp_dispatch_vertex()
1510 int numverts = (int)prim->numverts; in radeon_cp_dispatch_vertex()
1516 prim->prim, in radeon_cp_dispatch_vertex()
1517 prim->vc_format, prim->start, prim->finish, prim->numverts); in radeon_cp_dispatch_vertex()
1519 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { in radeon_cp_dispatch_vertex()
1521 prim->prim, prim->numverts); in radeon_cp_dispatch_vertex()
1537 OUT_RING(prim->vc_format); in radeon_cp_dispatch_vertex()
1538 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | in radeon_cp_dispatch_vertex()
[all …]
|
| D | radeon_ioc32.c | 217 u32 prim; member
237 || __put_user((void __user *)(unsigned long)req32.prim, in compat_radeon_cp_vertex2()
238 &request->prim)) in compat_radeon_cp_vertex2()
|
| /drivers/gpu/drm/r128/ |
| D | r128_state.c | 577 int prim = buf_priv->prim; in r128_cce_dispatch_vertex() local
607 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | in r128_cce_dispatch_vertex()
703 int prim = buf_priv->prim; in r128_cce_dispatch_indices() local
731 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | in r128_cce_dispatch_indices()
1370 if (vertex->prim < 0 || in r128_cce_vertex()
1371 vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { in r128_cce_vertex()
1372 DRM_ERROR("buffer prim %d\n", vertex->prim); in r128_cce_vertex()
1393 buf_priv->prim = vertex->prim; in r128_cce_vertex()
1426 if (elts->prim < 0 || in r128_cce_indices()
1427 elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { in r128_cce_indices()
[all …]
|
| D | r128_drv.h | 128 int prim; member
|
| /drivers/isdn/mISDN/ |
| D | dsp_core.c | 668 switch (hh->prim) { in dsp_function()
701 hh->prim = DL_DATA_IND; in dsp_function()
755 hh->prim = DL_DATA_IND; in dsp_function()
842 hh->prim = DL_ESTABLISH_CNF; in dsp_function()
858 hh->prim = DL_RELEASE_CNF; in dsp_function()
875 hh->prim = PH_DATA_REQ; in dsp_function()
906 hh->prim = PH_ACTIVATE_REQ; in dsp_function()
926 hh->prim = PH_DEACTIVATE_REQ; in dsp_function()
933 __func__, hh->prim, dsp->name); in dsp_function()
1016 if (hh->prim == DL_DATA_REQ) { in dsp_send_bh()
|
| D | stack.c | 31 __func__, hh->prim, hh->id, skb); in _queue_message()
114 hh->prim, ch->addr, ret); in send_layer2()
138 __func__, ch->nr, hh->prim, ch->addr, ret); in send_layer2()
153 lm = hh->prim & MISDN_LAYERMASK; in send_msg_to_layer()
156 __func__, hh->prim, hh->id, skb); in send_msg_to_layer()
175 __func__, dev_name(&st->dev->dev), hh->prim, in send_msg_to_layer()
185 __func__, dev_name(&st->dev->dev), hh->prim, in send_msg_to_layer()
190 __func__, dev_name(&st->dev->dev), hh->prim); in send_msg_to_layer()
|
| D | hwchannel.c | 160 hh->prim = PH_DATA_IND; in recv_Dchannel()
179 hh->prim = PH_DATA_E_IND; in recv_Echannel()
193 hh->prim = PH_DATA_IND; in recv_Bchannel()
320 hh->prim = pr; in queue_ch_frame()
|
| D | layer2.c | 136 l2up(struct layer2 *l2, u_int prim, struct sk_buff *skb) in l2up() argument
142 mISDN_HEAD_PRIM(skb) = prim; in l2up()
152 l2up_create(struct layer2 *l2, u_int prim, int len, void *arg) in l2up_create() argument
164 hh->prim = prim; in l2up_create()
190 if (hh->prim == PH_DATA_REQ) { in l2down_raw()
201 l2down(struct layer2 *l2, u_int prim, u_int id, struct sk_buff *skb) in l2down() argument
205 hh->prim = prim; in l2down()
211 l2down_create(struct layer2 *l2, u_int prim, u_int id, int len, void *arg) in l2down_create() argument
221 hh->prim = prim; in l2down_create()
273 l2mgr(struct layer2 *l2, u_int prim, void *arg) { in l2mgr() argument
[all …]
|
| D | tei.c | 285 teiup_create(struct manager *mgr, u_int prim, int len, void *arg) in teiup_create() argument
295 hh->prim = prim; in teiup_create()
1072 __func__, hh->prim, hh->id); in mgr_send()
1073 switch (hh->prim) { in mgr_send()
1155 __func__, hh->prim, hh->id); in check_data()
1158 if (hh->prim != PH_DATA_IND) in check_data()
1255 hh->prim, l2->ch.addr, ret); in mgr_bcast()
|
| D | dsp_cmx.c | 1333 hh->prim = PH_DATA_REQ; in dsp_cmx_send_member()
1561 thh->prim = DL_DATA_REQ; in dsp_cmx_send_member()
1900 hh->prim = PH_DATA_REQ;
1916 hh->prim = PH_DATA_REQ;
|
| D | l1oip_core.c | 899 switch (hh->prim) { in handle_dmsg()
1114 switch (hh->prim) { in handle_bmsg()
|
| /drivers/scsi/libsas/ |
| D | sas_port.c | 206 u32 prim; in sas_porte_broadcast_rcvd() local
212 prim = phy->sas_prim; in sas_porte_broadcast_rcvd()
215 SAS_DPRINTK("broadcast received: %d\n", prim); in sas_porte_broadcast_rcvd()
|
| /drivers/macintosh/ |
| D | via-pmu.c | 482 struct device_node* prim = in via_pmu_dev_init() local
485 if (prim) in via_pmu_dev_init()
486 prim_info = of_get_property(prim, "prim-info", NULL); in via_pmu_dev_init()
494 of_node_put(prim); in via_pmu_dev_init()
|
| /drivers/isdn/hardware/mISDN/ |
| D | hfcsusb.c | 221 switch (hh->prim) { in hfcusb_l2l1B()
300 switch (hh->prim) { in hfcusb_l2l1D()
335 ret = l1_event(dch->l1, hh->prim); in hfcusb_l2l1D()
366 ret = l1_event(dch->l1, hh->prim); in hfcusb_l2l1D()
|
| D | hfcpci.c | 1616 switch (hh->prim) { in hfcpci_l2l1D()
1646 ret = l1_event(dch->l1, hh->prim); in hfcpci_l2l1D()
1676 ret = l1_event(dch->l1, hh->prim); in hfcpci_l2l1D()
1699 switch (hh->prim) { in hfcpci_l2l1B()
|
| D | hfcmulti.c | 1834 hh->prim = PH_CONTROL_IND; in hfcmulti_dtmf()
3211 switch (hh->prim) { in handle_dmsg()
3260 ret = l1_event(dch->l1, hh->prim); in handle_dmsg()
3306 ret = l1_event(dch->l1, hh->prim); in handle_dmsg()
3353 switch (hh->prim) { in handle_bmsg()
|
| /drivers/scsi/aic94xx/ |
| D | aic94xx_sas.h | 599 u8 prim[4]; /* K, D0, D1, D2 */ member
|
| /drivers/gpu/drm/i810/ |
| D | i810_dma.c | 744 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); in i810_dma_dispatch_vertex() local
747 ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); in i810_dma_dispatch_vertex()
|