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Searched refs:reg32 (Results 1 – 8 of 8) sorted by relevance

/drivers/pci/hotplug/
Dpciehp_pci.c80 u32 reg32; in program_hpp_type2() local
111 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32); in program_hpp_type2()
112 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; in program_hpp_type2()
113 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpp_type2()
116 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32); in program_hpp_type2()
117 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; in program_hpp_type2()
118 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpp_type2()
121 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32); in program_hpp_type2()
122 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; in program_hpp_type2()
123 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpp_type2()
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/drivers/net/wireless/ath9k/
Dphy.c37 u32 reg32 = 0; in ath9k_hw_set_channel() local
92 reg32 = in ath9k_hw_set_channel()
96 REG_WRITE(ah, AR_PHY(0x37), reg32); in ath9k_hw_set_channel()
110 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ath9k_hw_ar9280_set_channel() local
117 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ath9k_hw_ar9280_set_channel()
118 reg32 &= 0xc0000000; in ath9k_hw_ar9280_set_channel()
163 reg32 = reg32 | in ath9k_hw_ar9280_set_channel()
167 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ath9k_hw_ar9280_set_channel()
177 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ath9k_phy_modify_rx_buffer() argument
184 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ath9k_phy_modify_rx_buffer()
Deeprom.c990 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local
1071 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | in ath9k_hw_set_def_power_cal_table()
1075 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
1080 reg32); in ath9k_hw_set_def_power_cal_table()
1117 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
1187 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | in ath9k_hw_set_4k_power_cal_table()
1191 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
1196 reg32); in ath9k_hw_set_4k_power_cal_table()
/drivers/pci/pcie/
Daspm.c139 u32 reg32; in pcie_check_clock_pm() local
150 pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, &reg32); in pcie_check_clock_pm()
151 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_check_clock_pm()
311 u32 reg32; in pcie_aspm_get_cap_device() local
315 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32); in pcie_aspm_get_cap_device()
316 *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; in pcie_aspm_get_cap_device()
323 latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; in pcie_aspm_get_cap_device()
326 latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; in pcie_aspm_get_cap_device()
360 u32 reg32; in pcie_aspm_cap_init() local
370 pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, &reg32); in pcie_aspm_cap_init()
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Dportdrv_core.c125 u32 reg32; in get_port_device_capability() local
132 pos + PCIE_SLOT_CAPABILITIES_REG, &reg32); in get_port_device_capability()
133 if (reg32 & SLOT_HP_CAPABLE_MASK) in get_port_device_capability()
/drivers/pci/pcie/aer/
Daerdrv_core.c538 u32 reg32; in aer_enable_rootport() local
552 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32); in aer_enable_rootport()
553 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32); in aer_enable_rootport()
554 pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, &reg32); in aer_enable_rootport()
555 pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, reg32); in aer_enable_rootport()
556 pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, &reg32); in aer_enable_rootport()
557 pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32); in aer_enable_rootport()
580 u32 reg32; in disable_root_aer() local
594 pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, &reg32); in disable_root_aer()
595 pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, reg32); in disable_root_aer()
/drivers/net/wireless/rtl818x/
Drtl8187_dev.c1366 u32 reg32; in rtl8187_probe() local
1367 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe()
1368 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe()
1369 switch (reg32) { in rtl8187_probe()
/drivers/net/
Dtg3.c1701 u32 reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) in tg3_phy_reset_5703_4_5()
1718 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) { in tg3_phy_reset_5703_4_5()
1767 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()