Searched refs:sync_offset (Results 1 – 6 of 6) sorted by relevance
289 u8 sync_offset; /* for reg. and nego.(low nibble) */ member1280 dcb->sync_offset = 0; in reset_dev_param()1413 dcb->sync_offset = 0; in build_sdtr()1415 } else if (dcb->sync_offset == 0) in build_sdtr()1416 dcb->sync_offset = SYNC_NEGO_OFFSET; in build_sdtr()1422 *ptr++ = dcb->sync_offset; /* Transfer period (max. REQ/ACK dist) */ in build_sdtr()1547 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in start_scsi()2689 DC395x_write8(acb, TRM_S1040_SCSI_OFFSET, dcb->sync_offset); in reprogram_regs()2704 dcb->sync_offset = 0; in msgin_set_async()2733 dcb->sync_offset = 0; in msgin_set_sync()[all …]
55 #define sync_offset flags macro
134 writeb(0, ®s->sync_offset); in mac53c94_init()166 writeb(0, ®s->sync_offset); in mac53c94_start()
471 uint8_t sync_offset:4; member478 uint8_t sync_offset:5; member
1170 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8); in qla1280_set_target_parameters()1175 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8); in qla1280_set_target_parameters()1960 nv->bus[bus].target[target].flags.flags1x160.sync_offset = 0x0e; in qla1280_set_target_defaults()1967 nv->bus[bus].target[target].flags.flags1x80.sync_offset = 12; in qla1280_set_target_defaults()2047 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8; in qla1280_config_target()2049 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8; in qla1280_config_target()
107 u_char sync_offset; member