Home
last modified time | relevance | path

Searched refs:t3_read_reg (Results 1 – 8 of 8) sorted by relevance

/drivers/net/cxgb3/
Dxgmac.c61 t3_read_reg(adap, ctrl); in xaui_serdes_reset()
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3_mac_reset()
140 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3_mac_reset()
162 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
175 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
185 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */ in t3b2_mac_reset()
244 u32 v = t3_read_reg(mac->adapter, reg); in disable_exact_filters()
247 t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ in disable_exact_filters()
255 u32 v = t3_read_reg(mac->adapter, reg); in enable_exact_filters()
258 t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */ in enable_exact_filters()
[all …]
Dt3_hw.c57 u32 val = t3_read_reg(adapter, reg); in t3_wait_op_done_val()
104 u32 v = t3_read_reg(adapter, addr) & ~mask; in t3_set_reg_field()
107 t3_read_reg(adapter, addr); /* flush */ in t3_set_reg_field()
128 *vals++ = t3_read_reg(adap, data_reg); in t3_read_indirect()
166 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
168 val = t3_read_reg(adap, in t3_mc7_bd_read()
173 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); in t3_mc7_bd_read()
175 val64 = t3_read_reg(adap, in t3_mc7_bd_read()
222 *valp = t3_read_reg(adapter, A_MI1_DATA); in t3_mi1_read()
283 *valp = t3_read_reg(adapter, A_MI1_DATA); in mi1_ext_read()
[all …]
Dmc5.c119 *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0); in dbgi_rd_rsp3()
120 *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1); in dbgi_rd_rsp3()
121 *v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2); in dbgi_rd_rsp3()
151 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX); in init_mask_data_array()
338 cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE; in t3_mc5_init()
424 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); in t3_mc5_intr_handler()
465 u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG); in t3_mc5_prep()
Dcxgb3_offload.c193 uiip->llimit = t3_read_reg(adapter, A_ULPRX_ISCSI_LLIMIT); in cxgb_ulp_iscsi_ctl()
194 uiip->ulimit = t3_read_reg(adapter, A_ULPRX_ISCSI_ULIMIT); in cxgb_ulp_iscsi_ctl()
195 uiip->tagmask = t3_read_reg(adapter, A_ULPRX_ISCSI_TAGMASK); in cxgb_ulp_iscsi_ctl()
197 val = t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ); in cxgb_ulp_iscsi_ctl()
201 val = t3_read_reg(adapter, A_TP_PARA_REG7); in cxgb_ulp_iscsi_ctl()
210 t3_read_reg(adapter, A_PM1_TX_CFG) >> 17); in cxgb_ulp_iscsi_ctl()
214 val = t3_read_reg(adapter, A_TP_PARA_REG2); in cxgb_ulp_iscsi_ctl()
229 ((t3_read_reg(adapter, A_TP_PARA_REG2)) >> in cxgb_ulp_iscsi_ctl()
238 if (val && (val != t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ))) { in cxgb_ulp_iscsi_ctl()
268 t3_read_reg(adapter, A_ULPTX_TPT_LLIMIT); in cxgb_rdma_ctl()
[all …]
Dael1002.c1178 status = t3_read_reg(phy->adapter, in xaui_direct_get_link_status()
1180 t3_read_reg(phy->adapter, in xaui_direct_get_link_status()
1182 t3_read_reg(phy->adapter, in xaui_direct_get_link_status()
1184 t3_read_reg(phy->adapter, in xaui_direct_get_link_status()
Dadapter.h258 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) in t3_read_reg() function
Dsge.c2656 t3_read_reg(adap, A_PL_CLI); /* flush */ in t3_intr()
2686 map = t3_read_reg(adap, A_SG_DATA_INTR); in t3b_intr()
2721 map = t3_read_reg(adap, A_SG_DATA_INTR); in t3b_intr_napi()
2778 unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE); in t3_sge_err_intr_handler()
2791 v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS); in t3_sge_err_intr_handler()
2848 u32 status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS); in sge_timer_cb()
Dcxgb3_main.c691 v = t3_read_reg(adap, A_TP_TM_PIO_DATA); in tm_attr_show()
1452 *p++ = t3_read_reg(ap, start); in reg_block_dump()