Searched refs:TRUE (Results 1 – 17 of 17) sorted by relevance
| /sound/oss/ |
| D | aedsp16.c | 270 #define TRUE 1 macro
515 return TRUE; in aedsp16_wait_data()
542 return ((aedsp16_read(port) == 0xaa) ? TRUE : FALSE); in aedsp16_test_dsp()
558 if (aedsp16_test_dsp(port) == TRUE) { in aedsp16_dsp_reset()
560 return TRUE; in aedsp16_dsp_reset()
705 return TRUE; in aedsp16_hard_write()
739 return TRUE; in aedsp16_hard_read()
791 return TRUE; in aedsp16_ext_cfg_write()
805 return TRUE; in aedsp16_cfg_write()
830 return TRUE; in aedsp16_init_mss()
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| D | os.h | 29 #define TRUE 1 macro
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| /sound/pci/echoaudio/ |
| D | layla24_dsp.c | 55 chip->bad_board = TRUE; in init_hw()
56 chip->has_midi = TRUE; in init_hw()
67 chip->digital_in_automute = TRUE; in init_hw()
79 err = set_professional_spdif(chip, TRUE); in init_hw()
151 TRUE); in load_asic()
294 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
346 incompatible_clock = TRUE; in dsp_set_digital_mode()
351 incompatible_clock = TRUE; in dsp_set_digital_mode()
389 err = write_control_reg(chip, control_reg, TRUE); in dsp_set_digital_mode()
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| D | gina24_dsp.c | 56 chip->bad_board = TRUE; in init_hw()
62 chip->digital_in_automute = TRUE; in init_hw()
90 err = set_professional_spdif(chip, TRUE); in init_hw()
156 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
283 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
300 incompatible_clock = TRUE; in dsp_set_digital_mode()
304 incompatible_clock = TRUE; in dsp_set_digital_mode()
341 err = write_control_reg(chip, control_reg, TRUE); in dsp_set_digital_mode()
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| D | echo3g_dsp.c | 62 chip->bad_board = TRUE; in init_hw()
63 chip->has_midi = TRUE; in init_hw()
81 chip->has_phantom_power = TRUE; in init_hw()
82 chip->hasnt_input_nominal_level = TRUE; in init_hw()
113 err = set_professional_spdif(chip, TRUE); in init_hw()
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| D | mona_dsp.c | 56 chip->bad_board = TRUE; in init_hw()
73 chip->digital_in_automute = TRUE; in init_hw()
85 err = set_professional_spdif(chip, TRUE); in init_hw()
155 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
364 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
380 incompatible_clock = TRUE; in dsp_set_digital_mode()
384 incompatible_clock = TRUE; in dsp_set_digital_mode()
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| D | layla20_dsp.c | 55 chip->bad_board = TRUE; in init_hw()
56 chip->has_midi = TRUE; in init_hw()
71 err = set_professional_spdif(chip, TRUE); in init_hw()
128 chip->asic_loaded = TRUE; in check_asic_status()
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| D | gina20_dsp.c | 51 chip->bad_board = TRUE; in init_hw()
57 chip->asic_loaded = TRUE; in init_hw()
68 err = set_professional_spdif(chip, TRUE); in init_hw()
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| D | mia_dsp.c | 55 chip->bad_board = TRUE; in init_hw()
59 chip->asic_loaded = TRUE; in init_hw()
61 chip->has_midi = TRUE; in init_hw()
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| D | darla20_dsp.c | 47 chip->bad_board = TRUE; in init_hw()
53 chip->asic_loaded = TRUE; in init_hw()
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| D | echoaudio_3g.c | 59 chip->asic_loaded = TRUE; in check_asic_status()
247 E3G_FREQ_REG_DEFAULT, TRUE); in load_asic()
390 incompatible_clock = TRUE; in dsp_set_digital_mode()
394 incompatible_clock = TRUE; in dsp_set_digital_mode()
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| D | darla24_dsp.c | 47 chip->bad_board = TRUE; in init_hw()
51 chip->asic_loaded = TRUE; in init_hw()
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| D | indigoio_dsp.c | 52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
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| D | indigodj_dsp.c | 52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
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| D | indigo_dsp.c | 52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
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| D | echoaudio_dsp.c | 106 chip->bad_board = TRUE; /* Set TRUE until DSP re-loaded */ in write_dsp()
129 chip->bad_board = TRUE; /* Set TRUE until DSP re-loaded */ in read_dsp()
167 chip->asic_loaded = TRUE; in check_asic_status()
338 chip->bad_board = TRUE; /* Set TRUE until DSP loaded */ in load_dsp()
919 chip->bad_board = TRUE; /* Set TRUE until DSP loaded */ in init_dsp_comm_page()
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| D | echoaudio.h | 156 #define TRUE 1 macro
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