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Searched refs:cr0 (Results 1 – 25 of 74) sorted by relevance

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/arch/powerpc/kernel/
Dcpu_setup_6xx.S186 cmpwi cr0,r10,7
189 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
190 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
327 cmplwi cr0,r3,0x8000 /* 7450 */
338 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
339 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
340 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
341 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
342 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
367 cmpwi cr0,r3,0x0200
[all …]
/arch/arm/include/asm/
Dvfpmacros.h10 MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg in toolkits()
14 MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd in toolkits()
20 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} in toolkits()
22 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
28 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
36 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
38 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
44 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
/arch/powerpc/kernel/vdso64/
Dgettimeofday.S55 crclr cr0*4+so
71 cmpwi cr0,r3,CLOCK_REALTIME
73 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
74 bne cr0,99f
103 cmpld cr0,r0,r8 /* check if updated */
110 cmpd cr0,r5,r7
123 crclr cr0*4+so
147 cmpwi cr0,r3,CLOCK_REALTIME
149 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
150 bne cr0,99f
[all …]
Ddatapage.S60 cmpli cr0,r4,0
61 crclr cr0*4+so
82 crclr cr0*4+so
Dcacheflush.S43 crclr cr0*4+so
60 crclr cr0*4+so
78 crclr cr0*4+so
/arch/powerpc/kernel/vdso32/
Dgettimeofday.S70 crclr cr0*4+so
93 cmpli cr0,r3,CLOCK_REALTIME
95 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
96 bne cr0,99f
128 cmpl cr0,r8,r0 /* check if updated */
137 cmpw cr0,r4,r7
150 crclr cr0*4+so
174 cmpwi cr0,r3,CLOCK_REALTIME
176 cror cr0*4+eq,cr0*4+eq,cr1*4+eq
177 bne cr0,99f
[all …]
Ddatapage.S60 cmpli cr0,r4,0
64 crclr cr0*4+so
82 crclr cr0*4+so
Dcacheflush.S43 crclr cr0*4+so
60 crclr cr0*4+so
78 crclr cr0*4+so
/arch/x86/kernel/
Defi_stub_32.S62 movl %cr0, %edx
64 movl %edx, %cr0
88 movl %cr0, %edx
90 movl %edx, %cr0
Drelocate_kernel_32.S52 movl %cr0, %eax
108 movl %cr0, %eax
111 movl %eax, %cr0
178 movl %cr0, %eax
180 movl %eax, %cr0
193 movl %eax, %cr0
/arch/x86/include/asm/
Dlguest.h81 u32 cr0; in lguest_set_ts() local
83 cr0 = read_cr0(); in lguest_set_ts()
84 if (!(cr0 & 8)) in lguest_set_ts()
85 write_cr0(cr0 | 8); in lguest_set_ts()
Dxor_64.h53 : "=&r" (cr0) \
68 : "r" (cr0), "r" (xmm_save) \
94 unsigned long cr0; in xor_sse_2() local
147 unsigned long cr0; in xor_sse_3() local
206 unsigned long cr0; in xor_sse_4() local
273 unsigned long cr0; in xor_sse_5() local
Dxor_32.h540 cr0 = read_cr0(); \
563 write_cr0(cr0); \
591 int cr0; in xor_sse_2() local
645 int cr0; in xor_sse_3() local
706 int cr0; in xor_sse_4() local
774 int cr0; in xor_sse_5() local
/arch/powerpc/mm/
Dslb_low.S67 cmpldi cr0,r9,0xf
175 crnot 4*cr0+eq,4*cr0+eq
183 cmpldi cr0,r9,0
187 cmpldi cr0,r9,0
191 cmpldi cr0,r9,0
263 crclr 4*cr0+eq /* set result to "success" */
282 crclr 4*cr0+eq /* set result to "success" */
/arch/x86/kernel/cpu/mtrr/
Dstate.c14 unsigned int cr0; in set_mtrr_prepare_save() local
31 cr0 = read_cr0() | X86_CR0_CD; in set_mtrr_prepare_save()
33 write_cr0(cr0); in set_mtrr_prepare_save()
Dcyrix.c130 u32 cr0; in prepare_set() local
140 cr0 = read_cr0() | X86_CR0_CD; in prepare_set()
142 write_cr0(cr0); in prepare_set()
/arch/s390/kernel/
Dmem_detect.c63 unsigned long flags, cr0; in detect_memory_layout() local
71 __ctl_store(cr0, 0, 0); in detect_memory_layout()
74 __ctl_load(cr0, 0, 0); in detect_memory_layout()
/arch/x86/boot/
Dcpucheck.c75 u32 cr0; in has_fpu() local
77 asm("movl %%cr0,%0" : "=r" (cr0)); in has_fpu()
78 if (cr0 & (X86_CR0_EM|X86_CR0_TS)) { in has_fpu()
79 cr0 &= ~(X86_CR0_EM|X86_CR0_TS); in has_fpu()
80 asm volatile("movl %0,%%cr0" : : "r" (cr0)); in has_fpu()
Dpmjump.S42 movl %cr0, %edx
44 movl %edx, %cr0
/arch/x86/kernel/acpi/realmode/
Dwakeup.S49 movl %cr0, %eax
51 movl %eax, %cr0
62 movl %eax, %cr0
115 movl %eax, %cr0
/arch/s390/lib/
Ddelay.c29 unsigned long mask, cr0, cr0_saved; in __udelay_disabled() local
35 cr0 = (cr0_saved & 0xffff00e0) | 0x00000800; in __udelay_disabled()
36 __ctl_load(cr0 , 0, 0); in __udelay_disabled()
/arch/arm/mach-sa1100/
Dssp.c163 ssp->cr0 = Ser4SSCR0; in ssp_save_state()
179 Ser4SSCR0 = ssp->cr0 & ~SSCR0_SSE; in ssp_restore_state()
181 Ser4SSCR0 = ssp->cr0; in ssp_restore_state()
/arch/x86/power/
Dcpu_32.c46 ctxt->cr0 = read_cr0(); in __save_processor_state()
107 write_cr0(ctxt->cr0); in __restore_processor_state()
Dcpu_64.c68 ctxt->cr0 = read_cr0(); in __save_processor_state()
103 write_cr0(ctxt->cr0); in __restore_processor_state()
/arch/arm/include/asm/hardware/
Dssp.h14 unsigned int cr0; member

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