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Searched refs:mfctl (Results 1 – 20 of 20) sorted by relevance

/arch/parisc/kernel/
Dbinfmt_elf32.c25 dst[48] = (elf_greg_t) mfctl(22); dst[49] = (elf_greg_t) mfctl(0); \
26 dst[50] = (elf_greg_t) mfctl(24); dst[51] = (elf_greg_t) mfctl(25); \
27 dst[52] = (elf_greg_t) mfctl(26); dst[53] = (elf_greg_t) mfctl(27); \
28 dst[54] = (elf_greg_t) mfctl(28); dst[55] = (elf_greg_t) mfctl(29); \
29 dst[56] = (elf_greg_t) mfctl(30); dst[57] = (elf_greg_t) mfctl(31); \
30 dst[58] = (elf_greg_t) mfctl( 8); dst[59] = (elf_greg_t) mfctl( 9); \
31 dst[60] = (elf_greg_t) mfctl(12); dst[61] = (elf_greg_t) mfctl(13); \
32 dst[62] = (elf_greg_t) mfctl(10); dst[63] = (elf_greg_t) mfctl(15);
Dentry.S122 mfctl %cr30, %r1
131 mfctl %cr30, %r1
201 mfctl %pcsq, spc
203 mfctl %pcoq, va
214 mfctl %pcsq, spc
220 mfctl %pcoq, va
238 mfctl %isr,spc
240 mfctl %ior,va
261 mfctl %isr,spc
267 mfctl %ior,va
[all …]
Dcache.c306 unsigned long space = mfsp(3), pgd = mfctl(25); in flush_user_cache_page_non_current()
417 alltime = mfctl(16); in parisc_setup_cache_timing()
419 alltime = mfctl(16) - alltime; in parisc_setup_cache_timing()
422 rangetime = mfctl(16); in parisc_setup_cache_timing()
424 rangetime = mfctl(16) - rangetime; in parisc_setup_cache_timing()
Dtime.c77 now = mfctl(16); in timer_interrupt()
212 unsigned long next_tick = mfctl(16) + clocktick; in start_cpu_itimer()
Dsyscall.S113 mfctl %cr30,%r1
128 mfctl %cr30,%r1 /* get task ptr in %r1 */
167 mfctl %cr11, %r27 /* i.e. SAR */
183 mfctl %cr30, %r1
515 mfctl %cr27, %r21 /* Get current thread register */
556 mfctl %cr27, %r1
Dtraps.c138 cr30 = mfctl(30); in show_regs()
139 cr31 = mfctl(31); in show_regs()
608 regs->gr[regs->iir & 0x1f] = mfctl(27); in handle_interruption()
610 regs->gr[regs->iir & 0x1f] = mfctl(26); in handle_interruption()
Dhpmc.S116 mfctl %cr14, %r4
Dreal2.S125 # define PUSH_CR(r, where) mfctl r, %r1 ! STREG,ma %r1, REG_SZ(where)
Dirq.c351 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); in do_cpu_irq_mask()
Dhead.S237 mfctl,w %cr11,%r10
Dperf_asm.S54 mfctl ccr,%r26 ; get coprocessor register
80 mfctl ccr,%r26 ; get coprocessor register
/arch/parisc/include/asm/
Delf.h275 dst[48] = mfctl(22); dst[49] = mfctl(0); \
276 dst[50] = mfctl(24); dst[51] = mfctl(25); \
277 dst[52] = mfctl(26); dst[53] = mfctl(27); \
278 dst[54] = mfctl(28); dst[55] = mfctl(29); \
279 dst[56] = mfctl(30); dst[57] = mfctl(31); \
280 dst[58] = mfctl( 8); dst[59] = mfctl( 9); \
281 dst[60] = mfctl(12); dst[61] = mfctl(13); \
282 dst[62] = mfctl(10); dst[63] = mfctl(15);
Ddelay.h32 start = mfctl(16); in __cr16_delay()
33 while ((mfctl(16) - start) < clocks) in __cr16_delay()
Dtimex.h17 return mfctl(16); in get_cycles()
Dsystem.h68 #define mfctl(reg) ({ \ macro
84 #define get_eiem() mfctl(15)
Dthread_info.h44 #define current_thread_info() ((struct thread_info *)mfctl(30))
Dassembly.h177 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
347 mfctl %cr27, %r3
391 mfctl %cr27, %r3
457 mfctl,w %cr11, %r1
468 mfctl %cr22, %r8
/arch/parisc/hpux/
Dgate.S41 mfctl %cr30,%r1
81 mfctl %cr11, %r27 /* i.e. SAR */
/arch/parisc/lib/
Dfixup.S32 mfctl 30,\t2
Dlusercopy.S49 mfctl %cr30,%r1