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/arch/blackfin/kernel/
Dsetup.c997 u_long csel, ssel; local
1002 ssel = bfin_read_PLL_DIV();
1003 if (ssel == cached_cclk_pll_div)
1006 cached_cclk_pll_div = ssel;
1008 csel = ((ssel >> 4) & 0x03);
1009 ssel &= 0xf;
1010 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1011 cached_cclk = get_vco() / ssel;
1022 u_long ssel; local
1033 ssel = bfin_read_PLL_DIV() & 0xf;
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