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Searched refs:tcr (Results 1 – 19 of 19) sorted by relevance

/arch/powerpc/sysdev/bestcomm/
Dbestcomm_priv.h264 reg = in_be16(&bcom_eng->regs->tcr[task]); in bcom_enable_task()
265 out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE); in bcom_enable_task()
271 u16 reg = in_be16(&bcom_eng->regs->tcr[task]); in bcom_disable_task()
272 out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE); in bcom_disable_task()
337 u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; in bcom_set_task_auto_start() local
338 out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task); in bcom_set_task_auto_start()
344 u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; in bcom_set_tcr_initiator() local
345 out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8)); in bcom_set_tcr_initiator()
Dfec.c128 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); in bcom_fec_rx_reset()
229 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); in bcom_fec_tx_reset()
Dgen_bd.c135 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); in bcom_gen_bd_rx_reset()
219 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); in bcom_gen_bd_tx_reset()
Data.c84 offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]); in bcom_ata_init()
Dbestcomm.c316 out_be16(&bcom_eng->regs->tcr[task], 0); in bcom_engine_init()
350 out_be16(&bcom_eng->regs->tcr[task], 0); in bcom_engine_cleanup()
/arch/arm/mach-rpc/
Ddma.c186 int tcr, speed; in iomd_set_dma_speed() local
197 tcr = iomd_readb(IOMD_DMATCR); in iomd_set_dma_speed()
202 tcr = (tcr & ~0x03) | speed; in iomd_set_dma_speed()
206 tcr = (tcr & ~0x0c) | (speed << 2); in iomd_set_dma_speed()
210 tcr = (tcr & ~0x30) | (speed << 4); in iomd_set_dma_speed()
214 tcr = (tcr & ~0xc0) | (speed << 6); in iomd_set_dma_speed()
221 iomd_writeb(tcr, IOMD_DMATCR); in iomd_set_dma_speed()
/arch/mips/kernel/
Dcevt-txx9.c50 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
55 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
83 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_mode()
107 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_next_event()
165 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_tmr_init()
167 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); in txx9_tmr_init()
/arch/arm/mach-davinci/
Dtime.c117 u32 tcr = davinci_readl(t->reg_base + TCR); in timer32_config() local
120 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); in timer32_config()
121 davinci_writel(tcr, t->reg_base + TCR); in timer32_config()
129 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; in timer32_config()
131 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; in timer32_config()
134 davinci_writel(tcr, t->reg_base + TCR); in timer32_config()
/arch/powerpc/sysdev/
Dppc4xx_gpio.c39 __be32 tcr; member
124 clrbits32(&regs->tcr, GPIO_MASK(gpio)); in ppc4xx_gpio_dir_in()
157 setbits32(&regs->tcr, GPIO_MASK(gpio)); in ppc4xx_gpio_dir_out()
/arch/mips/include/asm/
Dtxx9tmr.h15 u32 tcr; member
/arch/sh/include/asm/
Dsmc37c93x.h85 #define tcr iir macro
/arch/powerpc/platforms/52xx/
Dlite5200_pm.c180 out_be16(&bes->tcr[i], sbes.tcr[i]); in lite5200_restore_regs()
Dmpc52xx_pci.c81 u32 tcr; /* PCI + 0x6C */ member
318 out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); in mpc52xx_pci_setup()
/arch/m68k/include/asm/
Dbvme6000hw.h30 pad_q[3], tcr, member
/arch/powerpc/include/asm/
Dkvm_host.h158 u32 tcr; member
Dmpc52xx.h90 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */ member
/arch/mips/txx9/generic/
Dsetup.c480 __raw_writel(0, &tmrptr->tcr); in txx9_wdt_now()
485 &tmrptr->tcr); in txx9_wdt_now()
/arch/powerpc/kvm/
Demulate.c35 if (vcpu->arch.tcr & TCR_DIE) { in kvmppc_emulate_dec()
D44x_emulate.c214 vcpu->arch.tcr = vcpu->arch.gpr[rs]; in kvmppc_core_emulate_mtspr()