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Searched refs:ddc_base (Results 1 – 6 of 6) sorted by relevance

/drivers/video/i810/
Di810-i2c.c47 i810_writel(mmio, chan->ddc_base, (state ? SCL_VAL_OUT : 0) | SCL_DIR | in i810i2c_setscl()
49 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
58 i810_writel(mmio, chan->ddc_base, (state ? SDA_VAL_OUT : 0) | SDA_DIR | in i810i2c_setsda()
60 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
69 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
70 i810_writel(mmio, chan->ddc_base, 0); in i810i2c_getscl()
71 return ((i810_readl(mmio, chan->ddc_base) & SCL_VAL_IN) != 0); in i810i2c_getscl()
80 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK); in i810i2c_getsda()
81 i810_writel(mmio, chan->ddc_base, 0); in i810i2c_getsda()
82 return ((i810_readl(mmio, chan->ddc_base) & SDA_VAL_IN) != 0); in i810i2c_getsda()
[all …]
Di810.h252 unsigned long ddc_base; member
/drivers/video/nvidia/
Dnv_i2c.c33 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
40 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
49 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
56 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
65 if (NVReadCrtc(par, chan->ddc_base) & 0x04) in nvidia_gpio_getscl()
77 if (NVReadCrtc(par, chan->ddc_base) & 0x08) in nvidia_gpio_getsda()
127 par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e; in nvidia_create_i2c_busses()
131 par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36; in nvidia_create_i2c_busses()
135 par->chan[2].ddc_base = 0x50; in nvidia_create_i2c_busses()
Dnv_type.h43 unsigned long ddc_base; member
/drivers/video/riva/
Drivafb-i2c.c33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
69 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); in riva_gpio_getscl()
82 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); in riva_gpio_getsda()
134 par->chan[0].ddc_base = 0x36; in riva_create_i2c_busses()
135 par->chan[1].ddc_base = 0x3e; in riva_create_i2c_busses()
136 par->chan[2].ddc_base = 0x50; in riva_create_i2c_busses()
Drivafb.h38 unsigned long ddc_base; member