1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 3 4 /* 5 * OMAP2/3 PRCM base and module definitions 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 18 /* Module offsets from both CM_BASE & PRM_BASE */ 19 20 /* 21 * Offsets that are the same on 24xx and 34xx 22 * 23 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is 24 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. 25 */ 26 #define OCP_MOD 0x000 27 #define MPU_MOD 0x100 28 #define CORE_MOD 0x200 29 #define GFX_MOD 0x300 30 #define WKUP_MOD 0x400 31 #define PLL_MOD 0x500 32 33 34 /* Chip-specific module offsets */ 35 #define OMAP24XX_GR_MOD OCP_MOD 36 #define OMAP24XX_DSP_MOD 0x800 37 38 #define OMAP2430_MDM_MOD 0xc00 39 40 /* IVA2 module is < base on 3430 */ 41 #define OMAP3430_IVA2_MOD -0x800 42 #define OMAP3430ES2_SGX_MOD GFX_MOD 43 #define OMAP3430_CCR_MOD PLL_MOD 44 #define OMAP3430_DSS_MOD 0x600 45 #define OMAP3430_CAM_MOD 0x700 46 #define OMAP3430_PER_MOD 0x800 47 #define OMAP3430_EMU_MOD 0x900 48 #define OMAP3430_GR_MOD 0xa00 49 #define OMAP3430_NEON_MOD 0xb00 50 #define OMAP3430ES2_USBHOST_MOD 0xc00 51 52 53 /* 24XX register bits shared between CM & PRM registers */ 54 55 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 56 #define OMAP2420_EN_MMC_SHIFT 26 57 #define OMAP2420_EN_MMC (1 << 26) 58 #define OMAP24XX_EN_UART2_SHIFT 22 59 #define OMAP24XX_EN_UART2 (1 << 22) 60 #define OMAP24XX_EN_UART1_SHIFT 21 61 #define OMAP24XX_EN_UART1 (1 << 21) 62 #define OMAP24XX_EN_MCSPI2_SHIFT 18 63 #define OMAP24XX_EN_MCSPI2 (1 << 18) 64 #define OMAP24XX_EN_MCSPI1_SHIFT 17 65 #define OMAP24XX_EN_MCSPI1 (1 << 17) 66 #define OMAP24XX_EN_MCBSP2_SHIFT 16 67 #define OMAP24XX_EN_MCBSP2 (1 << 16) 68 #define OMAP24XX_EN_MCBSP1_SHIFT 15 69 #define OMAP24XX_EN_MCBSP1 (1 << 15) 70 #define OMAP24XX_EN_GPT12_SHIFT 14 71 #define OMAP24XX_EN_GPT12 (1 << 14) 72 #define OMAP24XX_EN_GPT11_SHIFT 13 73 #define OMAP24XX_EN_GPT11 (1 << 13) 74 #define OMAP24XX_EN_GPT10_SHIFT 12 75 #define OMAP24XX_EN_GPT10 (1 << 12) 76 #define OMAP24XX_EN_GPT9_SHIFT 11 77 #define OMAP24XX_EN_GPT9 (1 << 11) 78 #define OMAP24XX_EN_GPT8_SHIFT 10 79 #define OMAP24XX_EN_GPT8 (1 << 10) 80 #define OMAP24XX_EN_GPT7_SHIFT 9 81 #define OMAP24XX_EN_GPT7 (1 << 9) 82 #define OMAP24XX_EN_GPT6_SHIFT 8 83 #define OMAP24XX_EN_GPT6 (1 << 8) 84 #define OMAP24XX_EN_GPT5_SHIFT 7 85 #define OMAP24XX_EN_GPT5 (1 << 7) 86 #define OMAP24XX_EN_GPT4_SHIFT 6 87 #define OMAP24XX_EN_GPT4 (1 << 6) 88 #define OMAP24XX_EN_GPT3_SHIFT 5 89 #define OMAP24XX_EN_GPT3 (1 << 5) 90 #define OMAP24XX_EN_GPT2_SHIFT 4 91 #define OMAP24XX_EN_GPT2 (1 << 4) 92 #define OMAP2420_EN_VLYNQ_SHIFT 3 93 #define OMAP2420_EN_VLYNQ (1 << 3) 94 95 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 96 #define OMAP2430_EN_GPIO5_SHIFT 10 97 #define OMAP2430_EN_GPIO5 (1 << 10) 98 #define OMAP2430_EN_MCSPI3_SHIFT 9 99 #define OMAP2430_EN_MCSPI3 (1 << 9) 100 #define OMAP2430_EN_MMCHS2_SHIFT 8 101 #define OMAP2430_EN_MMCHS2 (1 << 8) 102 #define OMAP2430_EN_MMCHS1_SHIFT 7 103 #define OMAP2430_EN_MMCHS1 (1 << 7) 104 #define OMAP24XX_EN_UART3_SHIFT 2 105 #define OMAP24XX_EN_UART3 (1 << 2) 106 #define OMAP24XX_EN_USB_SHIFT 0 107 #define OMAP24XX_EN_USB (1 << 0) 108 109 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 110 #define OMAP2430_EN_MDM_INTC_SHIFT 11 111 #define OMAP2430_EN_MDM_INTC (1 << 11) 112 #define OMAP2430_EN_USBHS_SHIFT 6 113 #define OMAP2430_EN_USBHS (1 << 6) 114 115 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 116 #define OMAP2420_ST_MMC (1 << 26) 117 #define OMAP24XX_ST_UART2 (1 << 22) 118 #define OMAP24XX_ST_UART1 (1 << 21) 119 #define OMAP24XX_ST_MCSPI2 (1 << 18) 120 #define OMAP24XX_ST_MCSPI1 (1 << 17) 121 #define OMAP24XX_ST_GPT12 (1 << 14) 122 #define OMAP24XX_ST_GPT11 (1 << 13) 123 #define OMAP24XX_ST_GPT10 (1 << 12) 124 #define OMAP24XX_ST_GPT9 (1 << 11) 125 #define OMAP24XX_ST_GPT8 (1 << 10) 126 #define OMAP24XX_ST_GPT7 (1 << 9) 127 #define OMAP24XX_ST_GPT6 (1 << 8) 128 #define OMAP24XX_ST_GPT5 (1 << 7) 129 #define OMAP24XX_ST_GPT4 (1 << 6) 130 #define OMAP24XX_ST_GPT3 (1 << 5) 131 #define OMAP24XX_ST_GPT2 (1 << 4) 132 #define OMAP2420_ST_VLYNQ (1 << 3) 133 134 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 135 #define OMAP2430_ST_MDM_INTC (1 << 11) 136 #define OMAP2430_ST_GPIO5 (1 << 10) 137 #define OMAP2430_ST_MCSPI3 (1 << 9) 138 #define OMAP2430_ST_MMCHS2 (1 << 8) 139 #define OMAP2430_ST_MMCHS1 (1 << 7) 140 #define OMAP2430_ST_USBHS (1 << 6) 141 #define OMAP24XX_ST_UART3 (1 << 2) 142 #define OMAP24XX_ST_USB (1 << 0) 143 144 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 145 #define OMAP24XX_EN_GPIOS_SHIFT 2 146 #define OMAP24XX_EN_GPIOS (1 << 2) 147 #define OMAP24XX_EN_GPT1_SHIFT 0 148 #define OMAP24XX_EN_GPT1 (1 << 0) 149 150 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 151 #define OMAP24XX_ST_GPIOS (1 << 2) 152 #define OMAP24XX_ST_GPT1 (1 << 0) 153 154 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 155 #define OMAP2430_ST_MDM (1 << 0) 156 157 158 /* 3430 register bits shared between CM & PRM registers */ 159 160 /* CM_REVISION, PRM_REVISION shared bits */ 161 #define OMAP3430_REV_SHIFT 0 162 #define OMAP3430_REV_MASK (0xff << 0) 163 164 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 165 #define OMAP3430_AUTOIDLE (1 << 0) 166 167 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 168 #define OMAP3430_EN_MMC2 (1 << 25) 169 #define OMAP3430_EN_MMC2_SHIFT 25 170 #define OMAP3430_EN_MMC1 (1 << 24) 171 #define OMAP3430_EN_MMC1_SHIFT 24 172 #define OMAP3430_EN_MCSPI4 (1 << 21) 173 #define OMAP3430_EN_MCSPI4_SHIFT 21 174 #define OMAP3430_EN_MCSPI3 (1 << 20) 175 #define OMAP3430_EN_MCSPI3_SHIFT 20 176 #define OMAP3430_EN_MCSPI2 (1 << 19) 177 #define OMAP3430_EN_MCSPI2_SHIFT 19 178 #define OMAP3430_EN_MCSPI1 (1 << 18) 179 #define OMAP3430_EN_MCSPI1_SHIFT 18 180 #define OMAP3430_EN_I2C3 (1 << 17) 181 #define OMAP3430_EN_I2C3_SHIFT 17 182 #define OMAP3430_EN_I2C2 (1 << 16) 183 #define OMAP3430_EN_I2C2_SHIFT 16 184 #define OMAP3430_EN_I2C1 (1 << 15) 185 #define OMAP3430_EN_I2C1_SHIFT 15 186 #define OMAP3430_EN_UART2 (1 << 14) 187 #define OMAP3430_EN_UART2_SHIFT 14 188 #define OMAP3430_EN_UART1 (1 << 13) 189 #define OMAP3430_EN_UART1_SHIFT 13 190 #define OMAP3430_EN_GPT11 (1 << 12) 191 #define OMAP3430_EN_GPT11_SHIFT 12 192 #define OMAP3430_EN_GPT10 (1 << 11) 193 #define OMAP3430_EN_GPT10_SHIFT 11 194 #define OMAP3430_EN_MCBSP5 (1 << 10) 195 #define OMAP3430_EN_MCBSP5_SHIFT 10 196 #define OMAP3430_EN_MCBSP1 (1 << 9) 197 #define OMAP3430_EN_MCBSP1_SHIFT 9 198 #define OMAP3430_EN_FSHOSTUSB (1 << 5) 199 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 200 #define OMAP3430_EN_D2D (1 << 3) 201 #define OMAP3430_EN_D2D_SHIFT 3 202 203 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 204 #define OMAP3430_EN_HSOTGUSB (1 << 4) 205 #define OMAP3430_EN_HSOTGUSB_SHIFT 4 206 207 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 208 #define OMAP3430_ST_MMC2 (1 << 25) 209 #define OMAP3430_ST_MMC1 (1 << 24) 210 #define OMAP3430_ST_MCSPI4 (1 << 21) 211 #define OMAP3430_ST_MCSPI3 (1 << 20) 212 #define OMAP3430_ST_MCSPI2 (1 << 19) 213 #define OMAP3430_ST_MCSPI1 (1 << 18) 214 #define OMAP3430_ST_I2C3 (1 << 17) 215 #define OMAP3430_ST_I2C2 (1 << 16) 216 #define OMAP3430_ST_I2C1 (1 << 15) 217 #define OMAP3430_ST_UART2 (1 << 14) 218 #define OMAP3430_ST_UART1 (1 << 13) 219 #define OMAP3430_ST_GPT11 (1 << 12) 220 #define OMAP3430_ST_GPT10 (1 << 11) 221 #define OMAP3430_ST_MCBSP5 (1 << 10) 222 #define OMAP3430_ST_MCBSP1 (1 << 9) 223 #define OMAP3430_ST_FSHOSTUSB (1 << 5) 224 #define OMAP3430_ST_HSOTGUSB (1 << 4) 225 #define OMAP3430_ST_D2D (1 << 3) 226 227 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 228 #define OMAP3430_EN_GPIO1 (1 << 3) 229 #define OMAP3430_EN_GPIO1_SHIFT 3 230 #define OMAP3430_EN_GPT1 (1 << 0) 231 #define OMAP3430_EN_GPT1_SHIFT 0 232 233 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 234 #define OMAP3430_EN_SR2 (1 << 7) 235 #define OMAP3430_EN_SR2_SHIFT 7 236 #define OMAP3430_EN_SR1 (1 << 6) 237 #define OMAP3430_EN_SR1_SHIFT 6 238 239 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 240 #define OMAP3430_EN_GPT12 (1 << 1) 241 #define OMAP3430_EN_GPT12_SHIFT 1 242 243 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 244 #define OMAP3430_ST_SR2 (1 << 7) 245 #define OMAP3430_ST_SR1 (1 << 6) 246 #define OMAP3430_ST_GPIO1 (1 << 3) 247 #define OMAP3430_ST_GPT12 (1 << 1) 248 #define OMAP3430_ST_GPT1 (1 << 0) 249 250 /* 251 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 252 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 253 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 254 */ 255 #define OMAP3430_EN_MPU (1 << 1) 256 #define OMAP3430_EN_MPU_SHIFT 1 257 258 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 259 #define OMAP3430_EN_GPIO6 (1 << 17) 260 #define OMAP3430_EN_GPIO6_SHIFT 17 261 #define OMAP3430_EN_GPIO5 (1 << 16) 262 #define OMAP3430_EN_GPIO5_SHIFT 16 263 #define OMAP3430_EN_GPIO4 (1 << 15) 264 #define OMAP3430_EN_GPIO4_SHIFT 15 265 #define OMAP3430_EN_GPIO3 (1 << 14) 266 #define OMAP3430_EN_GPIO3_SHIFT 14 267 #define OMAP3430_EN_GPIO2 (1 << 13) 268 #define OMAP3430_EN_GPIO2_SHIFT 13 269 #define OMAP3430_EN_UART3 (1 << 11) 270 #define OMAP3430_EN_UART3_SHIFT 11 271 #define OMAP3430_EN_GPT9 (1 << 10) 272 #define OMAP3430_EN_GPT9_SHIFT 10 273 #define OMAP3430_EN_GPT8 (1 << 9) 274 #define OMAP3430_EN_GPT8_SHIFT 9 275 #define OMAP3430_EN_GPT7 (1 << 8) 276 #define OMAP3430_EN_GPT7_SHIFT 8 277 #define OMAP3430_EN_GPT6 (1 << 7) 278 #define OMAP3430_EN_GPT6_SHIFT 7 279 #define OMAP3430_EN_GPT5 (1 << 6) 280 #define OMAP3430_EN_GPT5_SHIFT 6 281 #define OMAP3430_EN_GPT4 (1 << 5) 282 #define OMAP3430_EN_GPT4_SHIFT 5 283 #define OMAP3430_EN_GPT3 (1 << 4) 284 #define OMAP3430_EN_GPT3_SHIFT 4 285 #define OMAP3430_EN_GPT2 (1 << 3) 286 #define OMAP3430_EN_GPT2_SHIFT 3 287 288 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 289 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 290 * be ST_* bits instead? */ 291 #define OMAP3430_EN_MCBSP4 (1 << 2) 292 #define OMAP3430_EN_MCBSP4_SHIFT 2 293 #define OMAP3430_EN_MCBSP3 (1 << 1) 294 #define OMAP3430_EN_MCBSP3_SHIFT 1 295 #define OMAP3430_EN_MCBSP2 (1 << 0) 296 #define OMAP3430_EN_MCBSP2_SHIFT 0 297 298 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ 299 #define OMAP3430_ST_GPIO6 (1 << 17) 300 #define OMAP3430_ST_GPIO5 (1 << 16) 301 #define OMAP3430_ST_GPIO4 (1 << 15) 302 #define OMAP3430_ST_GPIO3 (1 << 14) 303 #define OMAP3430_ST_GPIO2 (1 << 13) 304 #define OMAP3430_ST_UART3 (1 << 11) 305 #define OMAP3430_ST_GPT9 (1 << 10) 306 #define OMAP3430_ST_GPT8 (1 << 9) 307 #define OMAP3430_ST_GPT7 (1 << 8) 308 #define OMAP3430_ST_GPT6 (1 << 7) 309 #define OMAP3430_ST_GPT5 (1 << 6) 310 #define OMAP3430_ST_GPT4 (1 << 5) 311 #define OMAP3430_ST_GPT3 (1 << 4) 312 #define OMAP3430_ST_GPT2 (1 << 3) 313 314 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 315 #define OMAP3430_EN_CORE_SHIFT 0 316 #define OMAP3430_EN_CORE_MASK (1 << 0) 317 318 #endif 319 320